USB 3.1 controller IP core adds isochronous transfer support

September 30, 2021 // By Nick Flaherty
USB 3.1 controller IP core adds isochronous transfer support
System Level Solutions (SLS) has launched a eUSB 3.1 Gen2 Device Controller IP core with isochronous transfer support for broadcast and streaming FPGA designs.  

The isochronous transfer in the eUSB31SF boosts broadcast and streaming designs as well as space communication and telecommunication applications using transfer time-sensitive information. This provides guaranteed access to USB bandwidth with bounded latency.

The eUSB31SF IP core supports control, bulk, interrupt and isochronous transfers in SSP (USB 3.1 Gen 2), SS (USB 3.1 Gen 1), FS (12 Mbps) and HS (480 Mbps) modes.

The IP block uses the transceiver in an FPGA as a PHY layer, eliminating the need for an external PHY for USB 3.1. This reduces the I/O pin count and the bill of materials for a design.

The IP bloc supports simultaneous IN requests to different endpoints in SSP mode with up to 31 endpoints (1 default control endpoint +15 IN/OUT endpoints) under software control to select the number of buffers per endpoint based on the system requirements. A simple FIFO interface is used to transfer data.

“With the Isochronous support added to the eUSB 3.1 Gen2 Device Controller IP core applications requiring Guaranteed Bandwidth and Bounded Latency are easily realized in FPGA based products,” said Paresh Patel, CEO of SLS.

SLS provides the IP core along with add-ons such as a time limited License for the encrypted IP core and a reference design with software tools.

ww.slscorp.com

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