Xilinx has added HBM2e high bandwidth memory chips to its high end 7nm Versal FPGAs
An HBM2e controller and 32 port network switch has been added to the chiplets that sit on top of the FPGA fabric to interface to one or two HBM2e chips in the Versal HBM package. This provides up to 820Gbyte/s bandwidth to 32Gbytes of memory linked to the Versal FPGA chip.
Xilinx uses commercial memory chips with 1024bit wide interfaces from all three HBM suppliers for memory bound applications for data centre, wired networking, test and measurement, and aerospace and defence.
“The HBM2e components we source from multiple vendors but the controller and switch is our own IP,” said Mike Thompson, Senior Product Line Manager for Versal Premium and HBM ACAPs
The HBM2e chips are themselves stacks of memory die. The 8GB version uses a single stack with dummy slug for coplanarity and cooling, while the 16 and 32GB versions use two stacks.
The ACAP chips use CoWoS 3D chip assembly that is available from multiple packaging houses, says Thompson.
Having the memory controllers and PCIe interface on the chiplets allows the iterfac and memory to wake up in under 100ms to move data around while the rest of the device is configuring from the bitstream, he says. The other chiplets on the versal HBM include a mix of PAM4 and NRZ transceivers and ARM Cortex A72 processor cores and R5F real time controller cores.
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“Many real-time, high-performance applications are critically bottlenecked by memory bandwidth and operate at the edge of their power and thermal limits,” said Sumit Shah, senior director, Product Management and Marketing at Xilinx. “The Versal HBM series eliminates those bottlenecks to provide our customers with