Xilinx adds ML, incremental compile to FPGA design tool

June 22, 2021 // By Nick Flaherty
Xilinx adds ML, incremental compile to FPGA design tool
The latest version of the Vivado design tool for Xilinx FPGAs with a hierarchical, incremental compilation and machine learning support to speed up design closure.

Xilinx has added incremental and nested compilation as well as machine learning algorithms to the latest version of its FPGA design software.

The incremental compilation in the Vivado ML design tool allows parts of the FGPA fabric to be compiled independently at different times. This allows blocks of IP, for example from a partner or a customer, to be added entirely separately into a more complex design. Customers such as board maker Abaco are already using the tool for this, while test system developer Keysight is using it to allows different internal teams to develop separate blocks completely independently.

The tool both uses AI and is aimed at developers working on AI designs that would be implemented in its FPGAs in data centres or for edge computing.

“This is the next generation Vivado,” said Nick Ni, director of marketing, software and AI at Xilinx. “AI requires orders of magnitude more compute performance so there’s a huge need with designs with billions of transistors.”

“EDA is mainly heuristic algorithm designers and for them to adopt ML there is a talent gap so this is about how to apply ML for EDA tasks,” he said. “Xilinx has been working on the research for a while and finding a way to productise it. The design iteration aspect is something we are pretty excited about as ML has the intelligence to help pick the right strategy early on so it has big promise.”

The tool breaks the design down into smaller pieces from the beginning to the end into small reusable pieces. These are then compiled separately, speeding up the compile time of the final design by a factor of five, says Ni and boosting the quality of results (QoR).

“We are deploying a number of ML techniques, with an intelligent timing closure tool," he said. As the chip gets bigger timing closure is more challenging but this is a single button push. It automatically applies machine learning algorithms for congestion estimation and delay estimation to optimise the design based on past experience. This will  get closer to timing closure after 4 or 5 iterations then apply strategy prediction for the ‘last mile‘ closure, and try the top strategies from 60+ designs to find the appropriate approach to hit the target frequency.

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