At a pre-launch event held in London, recently elected CEO Victor Peng justified the need for the new architecture as a way to circumvent the demise of Moore's law, considering the ACAP as the mother of all future ASICs.
"It's not that we don't know how to go to the next node, but the economics of Moore's law have stopped working. Getting better performance or faster devices for cheaper is no longer true", the CEO said. This was hinting at the fact that for ASIC designers, it is becoming increasingly difficult to find the volumes that would justify the fixed value of an ASIC, without the possibility to optimize it for a wide mix of applications.
"The speed of innovation is outpacing silicon design cycles, and what do you do about this challenge?" Peng asked the audience, highlighting the need for adaptable chips.
The ACAP was presented as a major technology disruption for the industry, and Xilinx's most significant engineering accomplishment since the invention of the FPGA, no less. At its core, the ACAP has a new generation of FPGA fabric with distributed memory and hardware-programmable DSP blocks, a multicore SoC, and one or more software programmable, yet hardware adaptable, compute engines, all connected through a network on chip (NoC). Peng would remain evasive regarding the actual blend of fabric. "The way we create the bitstream is completely different, and the NoC enables above GHz flow control" the CEO said later during an interview with eeNews Europe.
The ACAP also has highly integrated programmable I/O functionality, ranging from integrated hardware programmable memory controllers, advanced SerDes technology and leading edge RF-ADC/DACs, to integrated High Bandwidth Memory (HBM) depending on the device variant. What makes it adaptive is that it can be changed at the hardware level to adapt to the needs of a wide range of applications and workloads, dynamically during operation.