sureCore opens low power memory compiler access

January 22, 2020 //By
memory compiler
SureCore Ltd is opening its low power memory compiler for 30 days to qualifying companies to evaluate the capabilities of its PowerMiser and EverOn standard SRAM IP products on low power metrics.

The new service will prove particularly useful for constraint and compute intensive SoC designs. The Compiler Access Program (CAP) is the newest service for the company's low-power SRAM IP that are implemented in CMOS and SOI processes for demanding imaging, artificial intelligence, IoT, medical & wearable applications. CAP is available to SoC designers to evaluate the performance and low power capabilities of SureCore's low power SRAM on 22nm, 28nm or 40nm process technology. Companies can apply for CAP at

"AI, imaging, IoT, medical & wearable devices all require enhanced power profiles. With SRAM integration levels continuing to rise, our standard products help deliver the power savings needed in these competitive market spaces. Through CAP, we're opening a low power memory test drive to optimize power budgets and manufacturability," explained Paul Wells, sureCore's CEO.

Companies qualifying for CAP receive a link and password plus the Compiler User Guide. Designers can then explore optimal performance/lowest power SRAM that meets project requirements. CAP will generate datasheets that cover detailed PPA information, including access times, dynamic power, and sleep/deep sleep/standby leakage power, based on the requested instances and operating environment.

PowerMiser and EverOn Low-Power SRAM IP are both silicon-proven, process independent, variability tolerant and features market leading dynamic & static power consumption, with EverOn delivering unparalleled low voltage operation.

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