150mm fab closures are a structural industry risk
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The phase-out of 150mm CMOS is not just a product change, it is a structural industry risk says Dr Ulrich Bretthauer at X-Fab
Manufacturers of electronic products and systems depend on reliable supply of integrated circuits, particularly in automotive, industrial, medical, and aerospace. Buyers of semiconductor devices, particularly in those specific sectors, depend heavily on a stable supply of integrated circuits. Therefore, the discontinuation by some foundries of 150mm (6-inch) wafer-based CMOS processes in the last few months is putting some companies in a difficult situation; it disrupts supply chains and has sent design engineers back to the drawing board, impacting strategic planning as a result.
The discontinuation of CMOS chip production on 150 mm wafers marked the end of processes at 0.6µm and larger, creating challenges for manufacturers across automotive, industrial, medical, and other sectors. These mature nodes remain widely used for analog and mixed-signal ICs, including sensor interfaces and power management chips. For many design teams, the relatively sudden announcement of 150 mm CMOS end-of-life (EOL) came with little warning. In some cases, the announcement triggered urgent meetings to evaluate stockpiles, initiate redesigns, and revalidate long-standing systems.
At the same time as the process nodes have been reduced in size, wafer sizes have increased from 150mm (6 inches) to 200mm (8 inches) and finally to 300mm (12 inches). In addition to Moore’s Law, this growth in size has made a decisive contribution to satisfying the growing demand for chips and at the same time reducing costs. While 300 mm wafers have become the norm for advanced nodes (<90 nm), many analog and mixed-signal applications remained on 150 mm wafers using mature nodes such as 0.6µm (see table 1).
Whilst 300mm wafers for advanced nodes have been the standard for more than two decades, it has become increasingly challenging to maintain production of CMOS processes on 150 mm wafers. As production volumes of 150 mm wafers have declined, the supply of direct and indirect materials has become more difficult and expensive. At the same time, equipment maintenance became more complex and indeed costly. As these associated costs could no longer be passed on to customers, many foundries were forced to discontinue 150mm wafer production.
According to the JEDEC standard J-STD-048 – the notification standard for product discontinuance – customers are given six months from the announcement to place final orders and twelve months for final deliveries. This tight timeline puts significant pressure on companies to quickly assess customer demand, secure last-time buys, and begin planning for replacements. In many cases, the only viable solution is to migrate the affected integrated circuits to a new process node – an effort that involves both technical and business considerations, especially when developing a custom ASIC.
These business considerations begin with an evaluation of economic viability. An ASIC should deliver a unique solution that optimizes system cost, performance, and PCB area, all while enabling added value through higher levels of integration. A technical evaluation needs to determine the appropriate node, evaluate the available feature set, and analyze both prototyping and wafer costs. Finally, a foundry partner must be selected based on its relevant track record, delivery commitment, manufacturing location, and a network of qualified service providers for design, test and supply chain management where applicable.
350nm CMOS on 200mm wafers: a logical migration path
Rather than jumping directly to sub-130 nm processes on 300mm wafers, many manufacturers are turning to 350nm or 180nm nodes on 200mm wafers. These processes strike a balance between efficiency, design simplicity, and long-term viability. Development costs are significantly lower than those associated with advanced nodes, thanks to simpler design flows and cheaper mask sets. In addition, the maturity of the 350nm node enables faster time to market with reduced verification overhead, supported by proven IP and stable PDKs that contribute to consistently high first-time-right success rates. Analog and high-voltage performance is often better at 350nm, with a broader range of device options than at more advanced nodes.
Wafer starts per month in 200 mm equivalent based on SEMI World Fab Forecast Q3’23
Both process nodes with 350nm and 180nm structure width are manufactured on 200mm wafers. Customers who have just experienced an EOL of processes on 150mm could be concerned about long-term availability and tend towards processes on 300 mm wafers. Despite these concerns about long term supply, the use of 300mm processes for low-volume products is not an economically viable option. That’s because development time and costs as well as mask costs are many times higher than with established 200mm processes. As the number of chips per wafer almost doubles when migrating from one wafer diameter to the next, a customer quickly falls below the minimum order quantity of a foundry when switching from 150mm to 300mm directly.
If the long-term availability of the processes is considered when deciding on a 350nm or 180nm CMOS technology, it is worth looking at the recent status of wafer deliveries. In the third quarter of 2023, technology nodes larger than 90 nm accounted for more than 38% of the monthly wafer volume produced. This means that the global supply chain for 200 mm wafers remains strong, ensuring continuous availability of materials and equipment.
With a long lifecycle and proven stability, the 350 nm node is ideally suited for analog, MEMS, and sensor-based systems, supporting integration of digital functionality sufficient for entry-level microcontrollers, such as ARM Cortex-M0, i8051, or RISC-V cores, along with embedded memory capabilities.
An ASIC on 350nm
X-Fab maintains an ecosystem called X-Chain that allows customers to focus on their specific core competences. The stability of X-Fab’s silicon-proven platforms enables high First-Time-Right success rates, while fast and cost-effective prototyping options support rapid production ramp-up.
The European production footprint enhances supply security and reduces exposure to geopolitical risks. Dual sourcing and a commitment to long-term supply of more than 15 years for its CMOS technologies from 350nm downwards ensures its customers long-term reliability and stability.
The ‘Sweet Spot’ for analog, power, and sensor applications
350 nm is the optimal technology node for analog-dominant ASICs. It supports high-voltage transistors up to 100 V and low-noise analog devices, with integration options for MEMS and sensor interfaces. The platform also includes automotive-grade non-volatile memory and robust I/O libraries, making it particularly well-suited for mixed-signal, sensor fusion, power management ICs, and motor control applications.
The phase-out of 150 mm CMOS is not just a product change; it is a structural industry risk. Companies relying on mature-node ASICs must act now to secure supply, avoid redesign bottlenecks, and retain system-level differentiation. X-Fab’s 350nm solutions on 200mm wafers offer a robust, cost-effective, and long-lived alternative – with a European supply base and ecosystem designed for stability and innovation.
Dr Ulrich Bretthauer is product marketing manager at X-fab
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