Samsung Electronics has launched a 3D IC packaging technology initially for SRAM memory at 7nm and beyond.
The eXtended-Cube (X-Cube) technology, to be discussed at the HotChips conference this week and on the video below, uses Samsung’s through-silicon via (TSV) technology and is aimed at applications such as 5G, artificial intelligence, high-performance computing, as well as mobile and wearable.
“Samsung’s new 3D integration technology ensures reliable TSV interconnections even at the cutting-edge EUV process nodes,” said Moonsoo Kang, senior vice president of Foundry Market Strategy at Samsung Electronics. “We are committed to bringing more 3D IC innovation that can push the boundaries of semiconductors.”
The X-Cube test chip built on 7nm uses TSV technology to stack SRAM on top of a logic die, freeing up space to pack more memory into a smaller footprint. The ultra-thin package design features significantly shorter signal paths between the dies for maximized data transfer speed and energy efficiency. Customers can also scale the memory bandwidth and density to their desired specifications.
Samsung X-Cube’s silicon-proven design methodology and flow are available now for advanced nodes including 7nm and 5nm. Building on the initial design, Samsung plans to continue collaborating with global fabless customers to facilitate the deployment of 3D IC solutions in next-generation high-performance applications.
- EIGHT 16GB DRAM DIE INTO 16GB PACKAGES FOR HPC
- 12-LAYER 3D-TSV CHIP PACKAGING TECHNOLOGY
- STACKED EVENT-BASED VISION SENSOR BOASTS HIGHEST HDR
- IMEC PROVIDES DRAM REVIEW, MULLS R&D DIRECTIONS
Other articles on eeNews Europe
- First seven customers for 5nm TSMC production
- Edge AI startup launches boards and tools
- 5nm ASIC designs start
- GaN-on-SiC pushes RF and power performance
- 5G MEMS antenna startup raises £2.3m