AI-enabled tool boosts chip interconnect
Arteris has launched its next generation of AI-enabled tool for its network on chip (NoC) interconnect IP.
FlexGen is designed to accelerate chip design by up to 10x, shortening and reducing iterations from weeks to days for greater efficiency.
AI heuristics reduce wire length by up to 30%, and latency by 10%. The tool can also improve chip or chiplet power efficiency in applications from automotive, datacentre, consumer electronics, communications and industrial. Such chips can have between 5 and 20 NoCs.
FlexGen builds on the physically aware FlexNoC 5 NoC IP technology and component library to automate the creation of high-performance network-on-chip (NoC) designs. Using AI-driven automation, FlexGen reduces manual adjustments by over 90%, enabling the generation of optimized NoC topologies in hours instead of days.
- Gigadevice NoC for chip interconnect
- AI NoC design with tiling mesh network
- Ncore cache coherent interconnect IP
FlexGen supports custom topologies, allowing designers to tailor the interconnect structure to specific performance requirements to achieve the 10% latency reduction with improved bandwidth. The ability to iterate NoC IP alternatives quickly enables early performance analysis during project planning stages.
Built-in physical awareness provides floorplan visualization and automatic timing closure assistance that significantly improves layout quality and productivity. Using multiple NoC IP alternatives can also reduce interconnect area, optimizing die size and providing valuable space for integrating additional IP blocks. Supporting a wide range of industry-standard protocols such as AMBA 5 ACE-Lite, AHB, and AXI adds scalability.
Dream Chip Technologies is using the tool to reduce design iterations from weeks to days, enabling rapid experimentation and faster development.
“We have used FlexGen on our Zukimo 1.1 automotive ADAS SoC with excellent results. FlexGen’s automated NoC IP generation allows us to create floorplan adaptive topologies with complex automotive traffic requirements within minutes, allowing for rapid experimentation to find design sweet spots, and to respond quickly to floorplan changes with almost push-button timing closure,” said Jens Benndorf, general manager of Dream Chip Technologies. “Our engineers are expert FlexNoC users, and we have been able to obtain superior power, performance and area (PPA) with shorter wire length and lower latencies using fewer resources with Arteris’ latest smart NoC IP product. We plan to use FlexGen in production to deliver SoCs faster and with higher quality.”
“High-performance computing and AI SoCs have become very complex, creating expanding requirements to meet the energy efficiency targets and project schedules,” said John Rayfield, corporate vice president of AI Silicon at AMD. “Given our experience of working closely with Arteris in the past, we are excited about the smart NoC FlexGen technology and its ability to support our next-generation product innovation.”
“FlexGen is the culmination of years of ground-breaking innovation to boost productivity while improving quality of results in order to overcome the exponential design challenges semiconductor companies and system houses face when creating today’s sophisticated electronics,” said Charles Janac, president and CEO of Arteris. “With 5 to 20 NoCs in an average SoC or chiplet, our customers need smart NoC IP that reduces design time while delivering superior quality of results, enabling faster innovation cycles for tomorrow’s products, which FlexGen delivers.”
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