Analog breakthrough from imec: 150 GSa/s DAC Boosts European 300 Gb/s Links
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Leuven, Belgium-based imec has announced a significant analog‑design breakthrough: a 7‑bit, 150 Giga‑samples‑per‑second (GSa/s) digital‑to‑analog converter (DAC) targeting up to 300 Gb/s per lane using PAM‑4 modulation. This paves the way for significantly faster interconnects in data center and hyper‑scale computing architectures, imec reports.
Built on imec’s advanced 5-nm FinFET CMOS platform, the DAC addresses growing challenges in high‑speed link design. As AI and cloud workloads become increasingly data-intensive, existing analog‑to‑digital and digital‑to‑analog conversion solutions have struggled to keep pace without ballooning power, latency, and signal‑integrity trade‑offs.
Peter Ossieur, imec’s program manager for high‑speed transceivers, emphasized that the new chip represents a compelling combination of speed and power efficiency — a rarity at this performance level. He explained that the design is “targeting data rates above 200 Gb/s and ultimately reaching 400 Gb/s per lane,” noting the use of 5 nm FinFET CMOS as a necessity in accommodating such performance.
150 GSa/s Milestone
Europe has lagged in leading‑edge DAC and ADC development compared to the United States and Asian players. Imec’s announcement is a strategic signal: domestic research and design can keep pace with global OEM demands in hyperscale data interconnects. The 150 GSa/s is a milestone. Previously only achievable in vertical integration labs or proprietary processes, imec’s prototype now takes that capability into mainstream FinFET CMOS.
The DAC’s context is crucial. Combined with low‑jitter femtosecond‑level clocking and PAM‑4 signaling, the analog design meets the industry’s move toward multi‑lane, 400 GbE and beyond. Thus, this device can be the foundation for future 300–400 GSa/s converters aimed at 100 GHz bandwidth links.
For European analog design teams and semiconductor OEMs, the advance represents an opportunity. Opportunity, imec’s process and architectural expertise can now underpin next‑generation SerDes and optical transceiver ASICs. At the same time, global rivals are moving toward 56 Tbit/s switch fabrics, AI accelerators, and exascale processors — all demanding ultra‑efficient, high‑speed I/O.
EU Chip Design
The pivot realigns European chip design. The focus shifts from IP licensing and legacy processes to high-speed mixed-signal innovation, crucial for next-gen data infrastructure. Key questions for execs: Who embeds this DAC first? And how will fab scalability and cost per die evolve?
imec’s statement that next steps will involve “doubling the sampling rate to 300 GSa/s and pushing bandwidth beyond 100 GHz” sets a clear trajectory. For pro engineers working on analog‑intensive high‑speed interfaces, this offers a rare, real‑world reference design rooted in European R&D. For executives, it signals that Europe can still generate analog IP leadership — on advanced nodes and with practical throughput gains.
More info: imec
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