Atomera’s dopant engineering reaches 50% of top chip makers

Interviews | October 16, 2023

By Peter Clarke

Atomera Inc. (Los Gatos, Calif.), a company founded by Robert Mears, the pioneer of the erbium-doped fibre amplifier, is making progress with its semiconductor dopant engineering technology.

The company is now engaged at an R&D level with about two-dozen chip manufacturers and recently signed a full commercial exploitation license allowing STMicroelectronics to use its Mears Silicon Technology (MST) manufacturing process.

ST will use the technology to improve smart power products although the claimed benefits for using MST extend much more broadly. Benefits can be seen across applications from conventional logic to analog, RF and RFSOI, and sense-amplifier peripheral circuitry for DRAM and for MRAM and ReRAM. The technique is also effective in improving the performance of high-K metal gate insulation. There are also benefits in CMOS image sensors.

The company’s progress so far has been slow and painstaking. But the company reckons that with the development of nanometer-scale processes and such techniques as gate-all-around transistors, the market is moving towards the company.

In 2001, after his work on the erbium-doped fibre amplifier, Mears founded Nanovis LLC to exploit the nanometer-scale engineering of materials. Subsequently there was a name change to Mears Technologies before the company changed again to become Atomera in 2016 and closed an initial public offering of shares. ST took an initial R&D license to investigate the technology in 2018 (see ST licenses Atomera manufacturing technology).

Half of the best

“These things take time. We are engaged with a number of companies,” said Mears, CTO of Atomera, in an interview with eeNews Europe. Although almost all of Atomera’s engagements are still in the R&D stage they represent about 50 percent of the world’s top chip manufacturers, the company claims.

MST is typically used to deposit partial monolayers of oxygen on the silicon wafer surface. The introduction of these layers can be used to help enhance mobility and current flow in the x-y plane and reduce it in the z-direction – which would typically be leakage current in transistors. The technique is also used to control doping profiles. This control is not just in the z-direction but can also be used to control lateral diffusion. Thus, the introduction of structured monolayers of oxygen within crystalline silicon can be used to create highly precise doping profiles.

The introduction of partial monolayers of oxygen (dark lines in silicon cross-section) allows precise control of carrier mobility and dopant diffusion. Source: Atomera Inc.

“Typically, a number of oxygen layers are all part of the process tailored to a particular application,” said Jeff Lewis, senior vice president of business development and marketing at Atomera.

Improved mobility and precise dopant control can then translate into higher performance transistors and smaller logic die sizes. In power applications improvements typically include lower “on” resistance, higher breakdown voltages, and die size reductions of 20 percent or more.

Given these advantages why hasn’t Atomera made more progress, sooner?

Mears acknowledges that trying to retrofit MST to semiconductor manufacturing processes with established doping profiles has not been easy. MST adds an additional process step or steps in manufacturing and in the past may have then required multiple R&D iterations to characterize the dopant profiles.

In at the beginning

“There’s no doubt the easiest point of adoption is at the beginning of a development cycle,” Mears said. In the past, the greater part of node development was a geometry shrink with minimal readjustment of doping profiles, he added.

Also, there was some distrust of Technical CAD (TCAD) tools to model these things but there’s now more precision in TCAD tools, Mears said. “Increasingly different process technologies are hitting a wall. So, simple scaling doesn’t apply anymore.”

The needed to use an epitaxial deposition tool was also an inhibition on the uptake of MST. “Historically what people wanted to do was shrink without requiring new tools,” said Mears. An epitaxial deposition tool is required to lay down the oxygen monolayers but the MST process is now supported on epi tools from Applied Materials, ASM and Kokusai Electric.

“Analog and power chipmakers were familiar with using ‘epi’ for bipolar transistors but when we started with CMOS, epitaxial deposition was not used,” said Mears. But increasingly it is being adopted at the leading-edge for compressive strain in source and drain and for silicon-germanium in the [transistor] channel, Mears stated. As a result, epitaxial deposition is becoming mainstream for transistor devices. This has removed another barrier to adoption.

Above all, the benefits from enhanced mobility and precision dopant positioning are becoming greater as geometries shrink. Reportedly the potential benefit in mobility from the use of MST in FinFETs is 10 percent. In GAA it advances to 15 percent or more. The potential performance benefit from dopant engineering in FinFETs is 15 percent but is 20 percent in GAA.

GAA and DRAM

“We are working with half of the world’s top semiconductor producers today and we have been doing work in GAA and in DRAM,” said Mears. In these two fields the number of players is small, but Lewis said: “There’s nothing we can announce.”

The company’s business model is based on technology licensing and royalties. As such the extended period gaining traction with the market has allowed Atomera to build an extensive patent portfolio with which to protect its technology. Since 2016 the company has filed more than 200 patents. This compares with 107 patents the company filed in the 13 years from 2003 to 2015. This should provide Atomera with patent protection into the 2040s.

The company has a set of white papers available from its website covering the advantages of MST in gate-all-around processes at 3nm/2nm, for switches in PMIC and RFSOI and in sense amplifiers for DRAM. There are also links to numerous peer-reviewed technical papers presented at conferences over many years.

“We’re working on some of the biggest problem areas that face logic and memory,” said Lewis.