Avnet ASIC launches low power 4nm design service
The ASIC design division of distributor Avnet Silica has launched a service for low power 4nm custom chips at TSMC.
The ASIC design service from Avnet is aimed at TSMC’s 4nm process technology and below for custom blockchain and AI edge computing. This follows the division’s launch in Europe in 2019 having operated from Israel since 1986.
The new design services are aimed at low-voltage conditions in the 4nm and below nodes. This includes recharacterizing standard cells for lower voltages, performing early RTL exploration to optimize power, performance, and area (PPA) tradeoffs, implementing an optimized clock tree, and utilizing transistor-level simulations to enhance the power optimization process.
The Avnet ASIC team built a full-scale design flow for PPA optimization of high-performance chips working at extremely low voltage and proved it in TSMC’s 4nm process. Performance, dynamic and leakage power estimations have been confirmed by post-silicon validation with a customer.
The customer defined the board solution and chip implementation concept, requirements, and executed front-end design based on library characterization for near-threshold voltage operation. Avnet ASIC then executed this design.
This follows the announcement in February that the Avnet ASIC team had been appointed as a Value Chain Aggregator (VCA) by TSMC. The appointment positions the Avnet ASIC team as a channel for TSMC ASIC customers, offering a full turnkey solution from design inception to layout and mass production using an EDA tool flow from Synopsys.
This competes with UK ASIC designers such as Sondrel which last week appointed a new chief executive and plans to de-list its shares.
“One of the industry challenges today is to optimize application performance by choosing the correct technology to meet customer needs,” said Pavel Vilk, GM and Head of Engineering at Avnet ASIC.
“TSMC’s 4nm process provides a great opportunity to save power and area without compromising target performance. However, operating at low voltages puts a lot of effort on voltage drop, which needs to be optimized through a holistic solution of board-package-chip design. Being a TSMC Value Chain Aggregator and a full turnkey partner to customers, we believe this new achievement could bring great value in helping our customers deliver their products to market competitively.”
Avnet ASIC is a business division of Avnet Silica, the European semiconductor specialist division of Avnet, and provides complete ASIC and COT services for design houses and electronic system companies that develop advanced SoC devices. It partners with TSMC, OSATs, leading IP and CAD vendors to provide services from specification to mass production with start-ups, OEMs, and international companies in hundreds of devices and a wide range of applications in various market segments.
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