Codasip boosts custom RISC-V performance in latest tool
Codasip in Germany has boosted its Studio RISC-V processor design toolset with improved compiler support and code density as well as full AXI bus support for high-performance designs
The Studio tool is at the heart of Codasip’s toolflow for customised processor cores around the RISC-V open instruction set architecture and the embedded tools needed to develop systems. The tool walks designers through the steps necessary to create a customised RISC-V processor from a Codasip embedded or application core design.
Studio 9.1 adds additional bus interfaces, now including full AXI which means Studio will readily support the development of more powerful application cores and multi-core systems.
Instruction memory size can dominate cost in embedded processors so code density improvements in Studio 9.1 will help to contribute to reducing overall system costs.
The update also include an LLVM-based SDK alongside a fast C/C++ compiler and Linker Support Package that were incorporated as part of Studio 9.0 launched in April 2021. This update significantly improves support for custom instructions in application cores running operating systems such as Linux. Another new feature brings support for ISA sub-targets that hugely reduce the maintenance of different SDKs for different ISA configurations.
“We are constantly evolving our tools offering and due to the nature of the diverse customer types, our projects and developments continue to help push our design tools further,” said Zdenēk Prikryl, CTO of Codasip. “Codasip is keen to simplify Design for Differentiation with our processor cores and tools which we have developed to make it easy for designers of any size to benefit from: enabling them to get high-performance, cost-effective and (importantly!) significantly differentiated products to market quickly and easily.”
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