Codasip looks to hire 100 RISC-V engineers in Bristol, Cambridge

September 21, 2021 // By Nick Flaherty
Codasip looks for 100 RISC-V engineers in Bristol, Cambridge
German RISC-V company Codasip is opening two RISC-V chip design centres in the UK in Bristol and Cambridge and looking for 100 engineers.

The RISC-V recruitment drive follows Imagination Technologies opening a chip design centre in Cambridge last week and an OpenRAN design centre in Bristol from US company Parallel Wireless.

Codasip is looking to hire over one hundred engineers over the coming quarters. The distributed design centre will be headed by newly appointed Director of the UK Design Centre, Simon Bewick, from Mindtech Global and Imagination, who recently joined Codasip’s management supervisory board. He was previously a Director of ASIC development at Ericsson.

“The UK has a wealth of talent in designing complex processors of all types and is a natural place for us to look to grow our technical tea,” said Dr Karel Masařík, Founder and CEO of Codasip, which is now based in Munich. “ We are already aggressively hiring in our other R&D sites to support significant new design wins and our expanded plans in high-end processor design and customization.”

“I am very pleased to welcome Simon to the Codasip team,” said Dr Ron Black, Executive Chairman of Codasip and former CEO of Imagination. “He brings a wealth of experience in CPUs, GPUs, and the design and verification of complex, high-performance, advanced node chips.”

Like most other chip design firms, Codasip supports fully remote working so applicants are also welcome from other places and other offices may be added in the future if there is a critical mass in a given location. These sites complement Codasip’s existing development teams in Sofia Antipolis France, Munich Germany, and Brno Czech Republic.

“With semiconductor scaling slowing down, we will see a golden age of specialized processor innovation,” said Bewick. “With its combination of processor development tools and RISC-V IP, Codasip is ideally placed to address this opportunity and I am excited to join the team.”

He joins Rupert Baines who joined Codasip as chief marketing officer after last year’s acquisition of chip IP designer UltraSoC, which had design centres in Cambridge and Bristol.

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“It will be very nice to have Codasip in Bristol. There’s the building of the general ecosystem and there’s potential to partner in the future,” said Peter Claydon, president of chip designer Picocom in Bristol. “There’s the informal sharing of resources such as labs that you find in Bristol where people are quite open to sharing things.”

Picocom has developed a multi-core chip and card for 5G OpenRAN systems. “We’ve used a vanilla RISC-V core from Andes with CEVA vector processors for the 5G but RISC-V now has its vector extensions and Codasip have a way of easily generating extensions so that will be interesting,” he said.

“We’re good friends with Codasip and clearly like-minded in that Cambridge is the place to be. We look forward to welcoming our new neighbours and we’re delighted with the positive momentum around the growth of a RISC-V ecosystem in the heartland of the other CPU player,” said David Harold, chief marketing officer at Imagination, which is also developing RISC-V cores.

Parallel Wireless opened the Open RAN office and lab in Bristol last week with a growing team with deep expertise in wireless infrastructure product architecture, design, implementation and integration of high performance commercial-off-the-shelf (COTS) compute platforms and applications.

www.codasip.com; www.picocom.com; www.imgtec.com; www.parallelwireless.com

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