Codasip, Codeplay to combine RISC-V and SYCL for open AI accelerator chips
Eight European organisations including Codasip and Codeplay are aiming to combine the RISC-V and SYCL standards for AI acceleration.
The SYCLOPS (Scaling extreme analYtics with Cross-architecture acceleration based on Open Standards) project, part of Horizon Europe, aims to provide open standards for AI accelerator hardware and software.
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SYCL is a cross-vendor, cross-architecture, data parallel programming model for all types of accelerators, including the open RISC-V instruction set architecture. SYCL was a key motivation for the acquisition of Codeplay by Intel.
SYCLOPS brings together consortium partners with expertise in computer architecture, programming languages, systems and runtimes, Big Data and High- Performance Computing. They are developing infrastructure tools for simple, fast, cost-efficient customization of RISC-V accelerators, platform tools such as compilers, runtime and interpreters for SYCL-based cross-architecture programming and parallel algorithms, profiling and porting tools for cross-architecture AI and analytics acceleration.
As well as Codeplay and RISC-V core developer Codasip, the partners include Cern, Eurecom, INESC-ID, Ruprecht-Karls University in Heidelberg, Hiro Microdatacentres and Accelom. They aim to demonstrate the tools for three applications in Autonomous Systems, High-Energy Physics and Precision Oncology.
The experience gained in SYCLOPS will also be used to contribute back to the SYCL and RISC-V standards; bringing together the two standards enables co-design in both standards, which in turn, will enable broader AI accelerator designs.
The project started in January 2023 with an online meeting, with the partners presenting their plans.
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