
Computer memory with a ‘bucket’ list
How 3D charge-coupled devices can promise an alternative to DRAM architectures – Imec research update
The traditional memory access in Van Neumann computer architectures is changing by new data Intensive- applications like AI and machine mearning. imec is researching how 3d CCD (Charge Coupled Devices) can overcome the typical processor to memory bottleneck. With this research imec is taking a different route by presenting a new memory concept that promises to meet all CXL type-3 block-addressable memory requirements: a charge-coupled device (CCD) with an IGZO-based channel arranged in a 3D NAND-like architecture.
From the research:
In a CCD device, a CCD register is written by loading charges into the various stages, which are made up of MOS capacitors that each can store one bit of information. This is essentially a serial operation, similar to a bucket brigade way of transport: the charge is fed into the first stage. Then it moves on to the next stage – controlled by several phase gates per stage (typically three or four). This movement continues until the first charge arrives at the output to be read out. The use of CCD as a memory device dates back to 1970 but was soon overshadowed by the byte-addressable DRAM. The technology was later introduced in the image sensor market, where it was further matured. Thus, the basic CCD technology is well-known and reliable. Being charge-based, it is also power efficient.
The novelty of imec’s concept is the specific 3D nature, making the CDD technology highly dense and very cost-effective. The proposed 3D architecture is inspired by 3D NAND technology, which has memory cells in all three dimensions. In a 3D NAND architecture, the cells are stacked to form a vertical string and are addressed by horizontal word lines. A ‘punch and plug’ process is used for fabrication: a word-line layer stack is grown, and cylindrical holes are formed by drilling down through the stack using advanced etch processes. NAND-specific layers, including a poly-Si channel, are then deposited along the sidewall of the hole.
Imec’s 3D CCD buffer memory concept follows a similar approach: the CCD registers, each composed of a string of MOS capacitor cells, are integrated into vertically aligned plugs. One key enabler is using an oxide semiconductor (such as IGZO) channel material instead of poly-Si. IGZO can be deposited via the technique of atomic layer deposition (ALD), allowing conformal deposition in such high aspect ratio structures. An additional advantage of using IGZO is the relatively long retention time. This relaxes the need to frequently refresh the memory, which is a major drawback of DRAM memories.
From what is possible with NAND Flash today (i.e., the capability of processing (at least) 230 layers), imec estimates that the 3D buffer memory can already provide five times more bit density than what (2D) DRAM is expected to offer by 2030. And 3D NAND Flash scaling hasn’t stopped: some of the memory chip makers promise to provide 1,000 layers by 2030. Hence, regarding bit density, the new block-addressable memory promises to vastly surpass DRAM. The imec researchers are currently investigating 3D implementations of the CCD structure, starting with a limited number of word lines.
More information on the research can be found here
