MENU

CXL3.1 controller IP for data centre chips

CXL3.1 controller IP for data centre chips

News |
By Nick Flaherty



CXL is continuing its push into data centre chips with CXL3.1 controller IP from Rambus.

The Compute Express Link (CXL) interconnect offers new ways for data centre to boost performance and efficiency with low-latency, high bandwidth connections and Rambus is tapping into its PCI Express 6 technology for the CXL3.1 controller IP.

CXL3.1 takes data rates up to 64 GT/s and offers multi-tiered switching as part of the interconnect fabric to allow for highly scalable memory pooling and sharing. These features will be key in the next generation of data centers to mitigate high memory costs and stranded memory resources while delivering increased memory bandwidth and capacity when needed.

The Rambus CXL3.1 Controller IP is a flexible design suitable for both ASIC and FPGA implementations. It uses the Rambus PCIe 6.1 Controller architecture for the CXL.io protocol, and it adds the CXL.cache and CXL.mem protocols specific to CXL.

The built-in, zero-latency integrity and data encryption (IDE) module delivers state-of-the-art security against physical attacks on the CXL and PCIe links. The controller can be delivered standalone or integrated with the customer’s choice of CXL3.1/PCIe 6.1 PHY.

“The performance demands of Generative AI and other advanced workloads require new architectural solutions enabled by CXL,” said Neeraj Paliwal, general manager of Silicon IP at Rambus. “The Rambus CXL 3.1 digital controller IP extends our leadership in this key technology delivering the throughput, scalability and security of the latest evolution of the CXL standard for our customers’ cutting-edge chip designs.”

www.rambus.com

Other CXL articles

 

If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :    eeNews on Google News

Share:

Linked Articles
10s