Microchip has launched a series of high performance serial attached memory controllers for the new Compute eXpress Link (CXL) specification and PCI Express 5.0 for data centre systems.
The SMC 2000 family of devices boosts DDR memory bandwidth and capacity with reliability and flexibility for next-generation artificial intelligence (AI) and machine learning (ML) chips.
The growing demands of AI and ML workloads, cloud computing and data analytics deployed on traditional parallel attached memory have reached an efficiency plateau due to the limitations of increased memory channels on a processor.
- ASIC enables industry’s first 512GB CXL memory module
- First open-source software kit for CXL memory
- First SoC with CXL 2.0 as memory accelerator
The design of the SMC 2000 devices enables CPUs, GPUs and SoCs to use CXL interfaces to connect either DDR4 or DDR5 memory without having to integrate a unique memory controller for each different type. The two DDR controllers in the chip provide more memory bandwidth per core and more memory capacity per core.
For example, using an SMC 2000 controller with DDR-4 memory, CPUs that only directly support DDR5 can now also re-use DDR-4 memory expansion. The dual signature authentication and Trusted Platform support, secure debug, and secure firmware update ensure the SMC 2000 CXL-based controller family also meets all critical storage and enterprise application security needs.
The company worked with Cadence Design Systems on the verification and compliance testing for the CXL specification.
“Cadence collaborated closely with Microchip on CXL verification and compliance testing, leveraging multiple Cadence Verification IP offerings to fine-tune the interconnect technology needed to advance performance for AI and HPC applications,” said Paul Cunningham, senior vice president and general manager of the System & Verification Group at Cadence. “Microchip’s release of the SMC 2000 CXL controller provides the memory bandwidth and capacity expansion required for the next generation of CPUs and GPUs to accelerate high-performance compute.”
The low-latency SMC 2000 16x32G and SMC 2000 8x32G memory controllers are designed to CXL 1.1 and CXL 2.0 specifications, DDR4 and DDR5 JEDEC standards and support PCIe 5.0 specification speeds. The SMC 2000 16x32G is the industry’s highest-capacity controller with 16 lanes operating at 32 GT/s and supports two channels of DDR4-3200 or DDR5-4800, resulting in a significant reduction in the required number of host CPU or SoC pins per memory channel.
Typical CXL attached memory modules include 512 GB of memory or more, providing an effective mechanism to increase the memory bandwidth available to processing cores. This provides data center operators the ability to deploy a broader range of ratios for memory to CPU cores depending on their actual application needs, giving improved memory usage.
“Having introduced the world’s first ASIC-based CXL DRAM module, along with an open-source software toolkit, Samsung will continue to drive the commercialization of CXL products in collaboration with our customers and partners to meet the growing demand for data-heavy applications,” said Cheolmin Park, vice president of Memory Global Sales & Marketing at Samsung Electronics, and director of the CXL Consortium.
- Marvell boosts CXL business with Tanzanite buy
- PCIe-CXL IP on TSMC 5nm process for storage and chiplets
- Rambus ships CXL 2.0 and PCIe 5.0 controllers with zero latency
The SMC 2000 has been designed into a memory module from SMART, and has support from Intel and AMD as well as server makers Dell and Lenovo.
“SMART has designed Microchip’s SMC 2000 into our CXL E3.S Memory Module (XMM) which is being adopted in new CXL-enabled platforms,” said Satya Iyer, SMART Modular’s vice president of Specialty Memory. “SMART has extensive experience launching new products based on emerging industry interconnect standards, such as OpenCAPI DDIMMs, and is now working closely with Microchip to enable XMMs as one of the CXL products in our portfolio.”
“We identified CXL as a disruptive technology early on and were integral to the standard’s definition. Microchip’s continued presence in the memory infrastructure market underscores our commitment to improving performance and efficiency for a broad range of SoC applications to support the increasing memory requirements of high-performance data centre applications,” said Pete Hazen, corporate vice president of Microchip’s Data Centre Solutions business unit.
“The CXL Consortium was founded with a vision to deliver to the industry an open standard that would accelerate next-generation data centre performance,” said Siamak Tavallaei, president, CXL Consortium. “We’re pleased to see Microchip, a valuable contributor to the CXL Consortium, deliver a CXL solution enabling a new ecosystem for high-performance, heterogeneous computing.”
To support our customers in building leading edge systems that are compliant with the CXL standard, the SMC 2000 comes with design-in collateral and our ChipLink diagnostic tool that provides extensive debug, diagnostics, configuration and analysis tools with an intuitive GUI.
The SMC 2000 16x32G will sample to select customers in Q3CY22.
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