DC-coupled, high-speed loopback relay hits 80 Gbps
Menlo Microsystems has released its enhanced MM5622 DC-coupled high-speed loopback relay, called the MM5622-01NBX. The upgraded version of the MM5622 delivers improved high-speed performance at 80 Gbps, enabling broader application coverage and increased performance margin for testing the latest high-speed digital interfaces.
The MM5622 loopback relay is available in a system-in-package (SiP) that fully integrates a driver, charge pump, and twelve high-performance switch channels, resulting in a significant reduction in board footprint for production loopback test systems. The MM5622 Ideal Switch supports the differential signal switching required for dozens of high-speed SerDes buses, now reaching data rates of up to 80 Gbps, with significant improvements in RF return loss, phase matching, insertion loss, and channel balancing. These enhancements enable substantially improved eye-diagram performance, which is essential for testing high-speed digital interfaces on numerous different high-performance systems-on-chips (SoCs) for both wafer sort and final test applications.
“We are exhibiting at SWTest for the first time and announcing this major performance upgrade to our already successful MM5622 loopback relay,” said Menlo Micro Co-Founder and Senior Vice President RF Business Unit Chris Giovanniello. “We remain committed to providing customised solutions to the biggest challenges facing test engineers as they try and validate the performance of some of the most complex SoCs. The MM5622 is a direct result of listening to our lead customers and adapting our products to meet their latest challenges.”
Menlo Micro is also introducing its latest software tools created to facilitate the design of production load boards using their high-speed loopback relay products. The Ideal Switch® HSIO SignalFlow Studio is an interactive web-based tool that helps test engineers connect their DUT and ATE tester pins into one of the many selectable MM56xx high-speed loopback relay products. The tool highlights possible connection paths, performance tradeoffs, and programming instructions, ensuring that test engineers achieve optimal performance from the device and reduce the risk of connection errors in the board design.
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