Intel backs RISC-V for Nios FPGA processor

Intel backs RISC-V for Nios FPGA processor

Technology News |
Intel's Nios V soft processor for its FPGAs uses the RISC-V: RV32IA architecture with atomic extensions, 5-stage pipeline and AXI4 interfaces. 
By Nick Flaherty

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Intel has developed a soft IP microcontroller core for its FPGAs using the oipen source RISV-V instruction set

The Nios V processor is the next generation of soft processor for Intel’s Cycline, Stratix and Aria FPGAs based on the open-source RISC-V Instruction Set Architecture. This processor is available in the Intel Quartus Prime Pro Edition Software starting with version 21.3. This follows the 32bit Nios II, launched over a decade ago by Altera in Quartus 8.

The Nios V is based on RISC-V: RV32IA architecture designed for performance, with atomic extensions, 5-stage pipeline, and AXI4 interfaces. 

The first version is the Nios V/m microcontroller. This has a benchmark performance of 0.46 DMIPS/MHz and 16 CoreMarks, making it about half the performance of an ARM M0+ core but comparable to other RV32 implementations. The benchmarking is perhaps less relevant as instruction extensions can be added in the FPGA fabric to boost performance for specific applications.

Intel is working on a general purpose application class processor called the Nios V/g to run operating systems such as Linux, presumably with a memory management unit.

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