JEDEC releases LPDDR6 targeting mobile and AI
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The JEDEC Solid State Technology Association has announced the publication of JESD209-6, the latest Low Power Double Data Rate 6 (LPDDR6) standard.
The JESD209-6 LPDDR6 standard will significantly enhance memory speed and efficiency for a range of applications, including mobile devices and AI systems. The new standard represents a significant advancement in memory technology, offering enhanced performance, power efficiency, and security.
To enable AI applications and other high-performance workloads, LPDDR6 employs a dual sub-channel architecture that allows for flexible operation while maintaining a small access granularity of 32 bytes. In addition, LPDDR6 offers a variety of new key features, including:
- 2 sub-channels per die and 12 data signal lines (DQs) per sub-channel to optimise channel performance capabilities.
- Each sub-channel includes four command/address (CA) signals, optimized to reduce ball count and improve data access speed.
- Static efficiency mode designed to support high-capacity memory configurations and maximize bank resource utilization
- Flexible data access, on-the-fly burst length control to support 32B and 64B access.
- Dynamic write NT-ODT (non-target on-die termination) enables the memory to adjust ODT based on workload demands, improving signal integrity.
To help meet ever-increasing demands for power efficiency, LPDDR6 operates with a lower voltage and lower power consumption VDD2-capable supply compared to LPDDR5. Additionally, LPDDR6 requires two power supplies for VDD2. Further power-saving features include alternating clock command inputs to enhance performance and efficiency. Dynamic Efficiency mode utilises a single sub-channel interface for low-power, low-bandwidth use cases, while support for both partial self and active refresh reduces refresh power usage. Dynamic Voltage Frequency Scaling for Low Power (DVFSL) lowers the VDD2 supply during low-frequency operation to minimise power consumption.
Security and reliability improvements over the previous version of the standard include:
- Per Row Activation Counting (PRAC) to support DRAM data integrity.
- Carve-out Meta mode is defined to enhance overall system reliability by allocating specific memory regions for critical tasks.
- Support for programmable link protection scheme and on-die error correction code (ECC).
- Capable of supporting Command/Address (CA) parity, error scrubbing, and memory built-in self-test (MBIST) for enhanced error detection and system reliability.
“LPDDR6 is the culmination of years of dedicated effort by members of the JC-42.6 Subcommittee for Low Power Memories,” said Mian Quddus, JEDEC’s Chairman of the Board of Directors. “By delivering a balance of power efficiency, robust security options and high performance, LPDDR6 is an ideal choice for next-generation mobile devices, AI and related applications to thrive in a power-conscious, high-performance world.”
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