Multicore and Worst-Case Execution Time (WCET) support for RISC-V
LDRA in the UK has added support for multicore processors using the RISC-V open instruction set architecture with worst case execution time (WCET) analysis to its tool suite.
A module automatically analyse shared memory, cache resource access, coherency issues, and measures worst case execution time to guarantee deterministic execution time for RISC-V processors that use hardware-based, multicore mitigation techniques such as those from Microchip, Synopsys and Andes Technology.
This allows developers of safety critical systems in automotive, aerospace and robotics applications to access and optimize performance across RISC-V-based multicore systems, automating WCET analysis and making it part of a continuous development cycle. Guaranteeing deterministic system performance is a continuous process: every code modification to core systems potentially requires a new WCET analysis to verify that changes have not introduced access issues that adversely increase execution time.
“We are contributing a lot of technologies for RISC-V verification,” said Jim McElroy, vice president of marketing at LDRA. “The LDRA tool suite includes key technology to make sure that engines can optimise the performance of RISC-V applications, mitigating a lot of the risk. We actually measure the timing on the target hardware, we don’t estimate. This uses individual probes outside of the application area, its all about the Deterministic performance.”
“What the application does is measure the effect of the shared resources so you could switch from one architecture to another to see the effect of the data coherency on the applications, whether it’s a low latency private cache or a shared memory.”
To maintain data coherency, mediation between cores for shared resources is required. This means a core using a shared resource can unintentionally lock out other cores needing access to the same resource, resulting in an uncertain additional latency. New RISC-V-based processors introduce capabilities in hardware to help mitigate multicore shared access and data coherency issues. For example, Microchip RISC-V processors allow developers to allocate low latency memory to each core with zero shared cache contention.
The LDRA tool suite now supports multicore RISC-V architectures that address this multicore contention in hardware. This support also gives developers access to the full suite of LDRA tools, including static and structural coverage analysis, MISRA compliance and extensive reporting capabilities, all while taking full advantage of RISC-V-based multicore mitigation capabilities.
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