Phase-change memory persists at VLSI Symposium

Technology News | May 8, 2023

By Peter Clarke

Phase-change memory (PCM) – the technology behind Intel’s now abandoned X-Point non-volatile memory – is still well-represented at the upcoming 2023 Symposium on VLSI Technology and Circuits. The conference is due to take place in Kyoto, Japan, June 11 to 16.

Intel’s phase-change memory business, called Optane, made a loss of $576 million on sales of $392 million in 2020, and excluded from a deal Intel made to sell its non-volatile memory and solid-state drive (SSD) business to SK Hynix for $9 billion announced in October 2020.

However, at SK Hynix researchers are due to present “The Chalcogenide-Based Memory Technology Continues : Beyond 20nm 4-Deck 256Gbit Cross-Point Memory,” in paper T9-1.

The team is due to present a cross-point memory based on a 20nm 1S1M (one selector, one memory) storage-class memory unit cell in a four-deck 256Gbit memory. But they do draw attention to problem.

The paper follows up on one presented by SK Hynix researchers at the International Electron Devices Meeting in 2018. In that paper SK Hynix presented a two-deck architecture at between 20 and 29nm node density with a read latency of less than 100ns in a 16Mbit test array.

Despite the “successful integration and excellent performance” the authors of the latest paper expect that the cross-point memory will have problems scaling because of susceptibility to thermal disturbance and smaller write program margin. The paper suggests that it may be possible to build a selector-only memory (SOM) as an alternative device for the next generation.

In the next paper (T9-2) a team drawn from SK Hynix and the Postech research institute are due to report the use of atomic layer deposition (ALD) to make an InTe binary ovonic threshold switch (OTS) and its combination with an HfOx buffer. The selector has a low off-leakage current of several nanoamperes, which when combined with the sub-nanometer ultrathin HfOx buffer reduces Ioff of to 1nA.

PCM microcontroller

In paper JFS5-3 authors from STMicroelectronics present “ASIL-D Automotive-Grade Microcontroller in 28nm FD-SOI with Full-OTA Capable 21Mbyte Embedded PCM Memory and Highly Scalable Power Management”

The paper is due to describe the first-ever ASIL-D automotive grade 0 capable microcontroller with an embedded 21Mbyte PCM with scalable power management. The microcontroller is part of ST’s Stellar family of automotive MCUs developed in proprietary 28nm FDSOI CMOS technology.

The PCM cell has an area of 0.019 square microns and could be doubled in size to 40.5Mbyte for enhanced over-the-air (OTA) mode to allow old and new application images to be held at the same time. The architecture allows power consumption to be scaled by more than four orders of magnitude, from a few amperes (high-performance configuration consumption-forward body biasing (FBB) temperature compensated) down to the 100μA range in the standby mode.

PCM neural networks

In an invited paper (TFS1-2) IBM researchers are set to present the use of phase-change memory array to implement neural networks. “Phase Change Memory-based Hardware Accelerators for Deep Neural Networks“ details deep neural networks with the multiply-accumulate (MAC) operations performed as parallel analog operations on large arrays of resistive devices – by using Ohm’s law and Kirchhoff’s current law.

The architecture avoids the movement of weights to offer a combination of low latency, high throughput and high energy efficiency.

The 14nm inference chip comprises multiple 512 x 512 arrays of PCM devices that can deliver software-equivalent inference accuracy for MNIST handwritten-digit recognition and recurrent long short-term memory (LSTM) benchmarks.