PICMG prepares microTCA standard for PCIe5.0
Over a decade after the original version of the microTCA board standard, the PICMG group is working on a new version to support more modern requirements.
The MicroTCA Working Group is working on the next generation of the MTCA architecture specifications with improvements for time sensitive and high bandwidth applications such as in high-energy physics as well as native support for PCI Express 5.0 used by the next generation of CPUs and FPGAs.
Future applications in industry require this higher bandwidth for image processing, signal detection, data acquisition. As current CPU speeds are limited by 80 W per slot power limit the support of more power for faster CPUs is on the task list as well. Future applications will also require other kinds of high- and low-speed fabrics paired with more flexibility in system design.
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The new version of the microTCA standard is particularly aimed at the science market for applications such as high frame rate megapixel detectors in photon experiments. The standard has become embedded in precision timing and synchronization equipment at particle accelerators at CERN, DESY, ESS, XFEL, KEK, SLAC, and others. The architecture and features are also consistent with the Modular Open Systems Approach (MOSA) being adopted as part of the US Department of Defense (DoD) electronic media acquisition policy.
Originally designed for edge telecom and networking as a reduced-footprint alternative to the popular AdvancedTCA specification, MicroTCA defines a backplane-based system for plug-in Advanced Mezzanine Cards (AdvancedMCs).
The core MTCA.0 base specification defines the mechanical and electrical characteristics of a MicroTCA backplane, card cage, power subsystem, cooling, and system management. Since ratification in 2011, the MTCA Base specification has been revised to support 10GBASE-KR and 40GBASE-KR4 Ethernet fabrics and spawned four additional sub-specifications adapted for data acquisition, control, and telemetry
A single MicroTCA system contains up to 12 AdvancedMCs slots and up to two MicroTCA Carrier Hubs (MCHs). MCHs provide intelligent platform management, power delivery, and facilitate switching over Ethernet, PCIe, and/or Serial RapidIO backplane interconnect fabrics.
The current committee is led by Kay Rehlich of DESY, Heiko Koerte of N.A.T. and Thomas Holzapfel from powerBridge.
“I am more than happy that the MicroTCA Working Group is so pro-actively addressing the recent demands. The new spec will find its way into many different vertical markets due to the flexibility of MicroTCA!”, says Koerte, VP and Director Sales & Marketing of NAT. “Applications in industrial automation, medical, telecommunication and networking, aerospace and transportation will not only benefit form these new features but also from how easily MicroTCA can be adapted to the exact needs. More than 16.500 MCHs just from NAT and many more I/O and compute cards delivered to the field speak for themselves.”
The PICMG MicroTCA family of specifications are available at www.picmg.org/wp-content/uploads/MicroTCA_Short_Form_Sept_2006.pdf.
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