Power-first: Some thoughts on ‘drowsy logic’ chip design

Feature articles | February 23, 2024

By admin

Giovanni Lostumbo, an IT design and energy-in-design specialist based out of Savanna, Illinois, USA, provides some thoughts and references on power-saving in chip design.

Abstract

Power-efficiency has been an increasing design consideration in virtually all new silicon in the past 15 years. Power-first¹ designs, however, typically appear only in niche applications such as IoT. A 2023 retrospective paper describing a research lab’s 2002 circuit, using a technique called “drowsy logic,” reviewed historical strategies to limit leakage in the context of foundries’ recent implementation of low-leakage FinFET and gate-all-around (GAA) technologies.^2,3 This review explores new research and additional industry applications of drowsy logic.

Keywords: Cache memory, Low power, Gate leakage

1 Introduction

In Computer Architecture Techniques for Power-Efficiency (2008), drowsy circuits are defined as “a new class of state-preserving leakage reduction techniques.”^4aWhen factored into the dynamic power equation P = CV²A f, it shows that there can be a cubic reduction in power consumed without a proportional reduction in performance,^4b especially in memory-bound or latency-tolerant regions of code.^4c When combined with sub-threshold voltage, it allows static power consumption to be greatly reduced.^4d,4e

The original 2002 technique involves a strategy, described as the “simple” policy, of placing all lines in a ‘drowsy’ mode using a single global counter, awakening it only when it is accessed.³ The performance trade-off was known to reduce leakage up to 85 percent while increasing run-time by just 0.62 percent in certain conditions (using 93 percent drowsy lines). The paper focused on advanced drowsy strategies in reducing latency due to L1’s time-critical cache, but suggested L2 cache strategies could use simpler techniques.

2 A Systems-Level Design

Direct mapping of both hardware and kernel resources offers a path to limit energy-intensive memory management caches. As a chip can be designed to operate in a more deterministic manner as in real-time operating systems (RTOS), use cases involving known application resource limits and scheduling can be increasingly factored into software-defined hardware (SDH), a decades old design goal.^5,6

A 2008 paper titled BTB Access Filtering: A Low Energy and High Performance Design describes lowering branch target buffers (BTBs) and using direct-mapped BTBs in superscalar processors with drowsy techniques in the filter buffer to limit predictor energy consumption by 92.7 percent, with up to a 10.8 percent performance trade-off⁷. One design concept that monolithic chips use is “holistic timing.”⁸ This is where multiple systems fit on a single die and operate within a certain window, including breaking partitions in the clock.

3. Drowsy logic in modern process nodes

References to “drowsy” circuits in industry publication news articles appear to have decreased in the mid 2010s. A keyword search of one well-known site – Semiconductor Engineering – turned up only two mentions of “drowsy” – in 2014 and 2015. “For memories, people are building additional operational modes for them, such as drowsy modes.”^9,10

A review in the ICSA@50 retrospective paper describes drowsy logic as “a form of voltage scaling.” It continues: “We proposed a design in which one can choose between two different supply voltages in each cache line, corresponding to normal supply voltage and a drowsy lower voltage. In effect we used a form of voltage scaling to reduce static power consumption.”²

The novel feature of this is that drowsy logic was applied to static power: “Such a dynamic voltage scaling or selection (DVS) technique has been used in the past to trade-off dynamic power consumption and performance. In this case, however, we exploit voltage scaling to reduce static power consumption.”³ New techniques utilizing hybrid or novel implementations of drowsy transistors in SRAM continue to be researched in academic labs.^{11, 12, 13}Furthermore, fabless semiconductor startups such as MicroMagic and R2 Semiconductor view Dynamic Voltage Frequency Scaling as a key IP licensing technology.¹⁴

4. Sub-threshold logic

The 2002 drowsy cache paper cites advances in short-channel effects: “Due to short-channel effects in deep-submicron processes, leakage current reduces significantly with voltage scaling. The combined effect of reduced leakage current and voltage yields a dramatic reduction in leakage power.”³The combined formula of DVS and Adaptive Body Biasing (ABB), led to a further 48% reduction in energy over DVS (drowsy logic) alone six months later.¹⁵Other labs have achieved similar results.^16,17Today, an 85% reduction in leakage power can be found in IoT devices which are designed for batteryless operation and energy-harvesting. Microcontrollers by companies such as Ambiq Micro are known to achieve a 13-fold reduction compared to other chips.¹⁸ IoT device-makers such as ONiO feature an integrated solar/RF/thermoelectric harvester and power management integrated circuit with low-power, asynchronous ROM/RAM.¹⁹ The ultra-low power of sub-threshold voltage combined with current drowsy cache techniques suggests mobile phones could one day run on solar power.

5. SRAM and in-memory computing

While drowsy modes of operation have been developed for SRAMs in both instruction and data caches, in high-performance computing (HPC), it may not yet have some of the advantages of state-of-the art memory such as spin-transfer torque (STT) MRAM and spin-orbital torque (SOT) MRAM. That is because they are designed to operate in low-data modes where speed is not as crucial to operation such as remote sensors with fixed interval telemetry.

6. Conclusion: Amdahl & Landauer’s Limits

The 2002 paper cites Amdahl’s Law in calculating the theoretical minimum.³ While it does acknowledge advances in short-channel effects and subsequent research detailed new avenues for advancing Moore’s Law,²⁰ Amdahl’s Law is more relevant to performance-oriented parallel, multi-core architectures. Power-saving sub-threshold voltage microprocessors and microcontrollers do not conventionally adopt such architectures, notwithstanding a move towards deeply embedded neural networks. “The lowest supply voltage at which a logic gate can operate while still acting as an amplifier is only a few times larger than k_BT /q.”²¹

As Scott Hanson recently stated that “Moore’s law is alive and well for the embedded world. We’re at a process node today that’s 22 nanometers,” one can speculate on the performance gains yet to come.²²

References:

¹https://semiengineering.com/a-power-first-approach/

²Drowsy Caches: Simple Techniques for Reducing Leakage Energy—A Retrospective ISCA@50 25-Year Retrospective

https://bpb-us-w2.wpmucdn.com/sites.coecis.cornell.edu/dist/7/587/files/2023/07/drowsy_retro.pdf

³Drowsy Caches: Simple Techniques for Reducing Leakage Power Krisztián Flautner, Nam Sung Kim, Steve Martin, David Blaauw, Trevor Mudge (2002) https://web.eecs.umich.edu/~manowar/publications/drowsy-caches-ISCA2002.pdf

⁴ Computer Architecture Techniques for Power-Efficiency, Stefanos Kaxiras & Margaret Martonosi (^aCh. 5.3)(^bCh. 3.1)(^cCh. 1.2.1)(^dCh. 5.1.1)(^eCh. 5.4.1) Morgan & Claypool Press 2008

⁵Software-Defined Hardware Architectures 05/2023 https://semiengineering.com/software-defined-hardware-architectures/

⁶Deterministic Clock Gating for Microprocessor Power Reduction 2003 https://engineering.purdue.edu/~vijay/papers/2003/dcg.pdf

⁷BTB Access Filtering: A Low Energy and High Performance Design Shuai Wang, Jie Hu, and Sotirios G. Ziavras Department of Electrical and Computer Engineering New Jersey Institute of Technology (2008) https://web.archive.org/web/20090920084956id_/https://web.njit.edu:80/~sw63/pub/ISVLSI_BAF_2008.pdf

⁸Why Chiplets Don’t Work For All Designs 09/2023

https://semiengineering.com/why-chiplets-dont-work-for-all-designs/

⁹S-L Power Modeling Gains Steam 08/2014

https://semiengineering.com/system-level-power-modeling-activities-get-rolling/

¹⁰With Responsibility Comes Power 02/2015

https://semiengineering.com/with-responsibility-comes-power/

¹¹ Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC 2016 https://cseweb.ucsd.edu/~jzhao/files/darlsilicon-noc-tvlsi2016.pdf

¹² Design the efficient SRAM circuit using 4transistor with sleepy logic International Journal of Pure and Applied Mathematics Volume 118 No. 20 2018, 115-123 https://acadpubl.eu/hub/2018-118-21/articles/21b/15.pdf

¹³Design and Implementation of Low Power SRAM Using Highly Effective Lever Shifters 2021 https://scholar.uwindsor.ca/cgi/viewcontent.cgi?article=9892&context=etd