Raaam signs lead licensee for SRAM replacement technology

Interviews | July 23, 2024

By Peter Clarke

Memory IP licensing startup Raaam Memory Technologies Ltd. (Petah Tikva, Israel) has signed a major fabless chip company as its lead partner to help it develop an alternative to static RAM.

Raaam calls the technology Gain-Cell Random Access Memory (GCRAM) and claims it can provide a 50 percent area saving versus SRAM and consume 10 percent of the power of SRAM.

Raaam had already disclosed that unnamed multinational semiconductor company was an investor in its US$4 million seed financing round (see Startup gets funds for cost effective low-power on-chip memory). Raaam executives have now told eeNews Europe that the strategic investor – a fabless chip company and one of TSMC’s top ten customers – has become a licensee. Raaam said it is still under a non-disclosure agreement not to reveal the identity of the company. Having already designed test chips on a 16nm FinFET process, Raaam is working with the licensee and with foundry TSMC on a 5nm evaluation with a plan to have first 5nm GCRAM silicon in 1Q25.

“That would be a test chip but it could become a hard macro available for licensing,” said Robert Giterman, CEO and cofounder of Raaam. “We are also working on a compiler so that custom memory blocks can be developed and we would expect TSMC to include the memory as part of their IP library,” he said

Swiss connection

Founded in May 2021 by PhDs from Bar-Ilan University and the Swiss Federal Institute of Technology, Lausanne, the company’s thesis is that SRAM is hitting a wall and is not scaling effectively either in area or voltage beyond about 5nm or 3nm. With use cases such as AI and ML requiring large amounts of on-chip memory – from 40 percent up to 70 percent and beyond – it has become beneficial to find an alternative memory, the company asserts.

The company has alighted on a CMOS-compatible three-transistor dynamic RAM and worked to extend the refresh period substantially. This results in an embedded memory that occupies significantly less area than SRAM but that – with peripherals and memory control – can be a drop-in replacement for SRAM.

Single- and two-ported blocks can have a standard SRAM interface but with other interface options available and with blocks of up to 2Mbits in size.

In terms of power consumption not only is there less circuity but also Raaam has demonsrated a Vmin of 450mV in a 16nm FinFET manufacturing process versus 700mV for standard on-chip SRAM.In terms of performance GCRAM arrays can still return results within a single-cycle delay times, Giterman said. He added that there are trade-offs. “We can prioritize density over performance or we can increase performance at the cost of area.”

Embedded DRAM is even denser than GCRAM but the primary reason why it has not been able to step up to this task is that substantial capacitors are required for a 1T1C bit cell and this requires a change to logic CMOS and additional mask layers. The incompatibility with standard CMOS and yield impacts, particularly in leading-edge manufacturing processes, has more or less killed off eDRAM offerings.

FDSOI?

There is nothing that limits GCRAM to FinFET manufacturing processes and their gate-all-around descendents or to TSMC, said Giterman. “We have done some fully-depleted silicon-on-insulator [FDSOI] research chips and that does offer some advantages with back biasing to further reduce leakage current.”

Eli Leizerovitz, chief business officer, also pointed out that Raaam had been inducted into the ‘Intel Ignite’ startup accelerator program and so its technology is also known to that chip company.

However, to get Raaam to market, more funds are needed. Leizerovitz said the company is in the process of raising about US$10 million to US$15 million in a Series A round of equity financing. “That’s about the right amount if we are proceeding on a single manufacturing process front,” said Giterman “If we choose to try and do more things at once we may need a bit more,” he said.