Researchers push for fault tolerant quantum computer in 2024
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Researchers in France have developed a quantum error correction architecture that they say could lead to practical fault tolerant quantum computers by the end of 2024.
The research led by Alice & Bob in France with the Inria national research institute reduces number of qubits for a useful quantum computer with novel approach to error correction low-density parity-check (LDPC) codes on cat qubits.
Using LDPC codes for cat qubits could encode 100 highly reliable logical qubits with as little as 1,500 physical qubits, establishing feasible path to useful business applications. The research enables the implementation of gates as well as the use of short-range connectivity on quantum chips.
The resulting reduction in overhead required for quantum error correction will allow the operation of 100 high-fidelity logical qubits (with an error rate of 10-8) with as little as 1,500 physical cat qubits which are available in systems today.
Alice & Bob has already taped out a chip that would encode their first logical qubit prototype, Helium 1, with enabling 100 logical qubits with as little as 1,500 physical qubits to run fault-tolerant algorithms. IBM also offers up to 1,121 physical qubits in its system and has been researching LDPC techniques.
- Alice & Bob tape out 16 qubit quantum processor
- Bob and Alice enable Long-distance quantum teleportation
- Quantum entanglement (of Alice and Bob) on-a-chip
“This new architecture using LDPC codes and cat qubits could run Shor’s algorithm with less than 100,000 physical qubits, a 200-fold improvement over competing approaches’ 20 million qubit requirement.” said Théau Peronnin, CEO of Alice & Bob. “Our approach makes a quantum computer more realistic in terms of time, cost and energy consumption, demonstrating our continued commitment to advancing the path to impactful quantum computing with error corrected, logical qubits.”
“Over 90% of quantum computing value depends on strong error correction, which is currently many years away from meaningful computations,” said Jean-François Bobier, Partner and Director at the Boston Consulting Group. “By improving correction by an order of magnitude, Alice & Bob’s combined innovations could deliver industry-relevant logical qubits on hardware technology that is mature today.”
The cat qubit approach being driven by Alice and Bob already enables logical qubit designs that require significantly fewer qubits as a result of the inherent protection from bit flip errors. In a previous paper by Alice & Bob and CEA, researchers demonstrated how it would be possible to run Shor’s algorithm with 350,000 cat qubits, a 60-fold improvement over the state-of-the art.
LDPC codes are a class of efficient error correction codes that reduce hardware requirements to correct errors occurring in a quantum computer. By using LDPC codes on a cat-qubit architecture, this latest work not only shows how the qubit footprint of a fault tolerant quantum computer could be further reduced but overcomes two key challenges for the implementation of quantum LDPC (qLDPC) codes.
Alice & Bob has also developed a simpler architecture for a fault-tolerant set of parallelizable logical gates without additional hardware complexity for a quantum computer design.
The paper is available on arXiv,
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