Synopsys launches PCIe 7.0 end to end IP
Synopsys has launched a complete set of IP for end-to-end PCI Express 7.0 designs, including the verification IP.
The IP comes as PCIe 7.0 reaches version 0.5, which is the point at which Synopsys has previously launched its IP for chip designers.
The PCIe 7.0 IP covers IP covers the SERDES PHY physical layer, controller, encryption module and verification IP, ready for chips on the market in the second half of 2025.
“We have been designing the PCIe technology or 20 years and every time the technology reaches 0.5 we make the announcement so you could say we started designing this 20 years ago,” Priyank Shukla, principal product manager for interface IP at Synopsys tells eeNews Europe.
First review draft of PCIe 7.0 specification
PCIe 7.0 doubles the bandwidth to 512Gbyte/s but also increases the power dissipation. Data centres and AI are expected to see an increase of 80% in power consumption, so there is a key focus on reducing the power in the IP.
“The silicon needs to be demonstrated when the standard reaches 0.5 and we showed the PHY at 128Gbit/s last year so we have the proof point today,” he said.
“5.0 to 6.0 was a bigger leap as it went to PAM4 signalling,” he said. “6.0 to 7.0 is more of an incremental leap. Form a controller point of view very little is expected to change. We are the only IP company on the board of PCI-SIG so that gives us an understanding of the specification so we know what’s coming.”
“We will go through a progression as the standard solidifies and the ecosystem understands that. Verification IP is where it starts.”
“Designers are aiming at H1 25 for tape out and that’s when the design views will be made available, and we are making the IP available in 5 and 3nm and we are considering the interest in other nodes.”
“We address the whole ecosystem and everyone has different optimisations. Some customers are developing chiplet, some are developing monolithic devices.”
The PHY can also be used for specifications such as CXL for distributed memory and UCIe for chiplet interconnect.
Shukla points to the focus on optimising power consumption that has come from the previous generation IP.
“We are improving power efficiency by 50%, this is at each layer,” he said. “PCIe 6.0 64GT/s in the field has allowed the power to be optimised, for example we have optimised the logic in the controller with less gates.”
“But the power depends a lot on the channel. If the channel losses are higher the SERDES has to do more compensation so it will use more power. This will also run over optical links.”
PCIe 7.0 includes RAS-DES from PCIe 6.0, where Synopsys has over 75 licenses, to simplify debug. as well as ARM confidential computing (CCA) and AES-GCM packet encryption for FIPS 140-3 certification. Competitor Intel, customers Kandou, Microchip and Astera Labs and partner Samtec have commented on the launch.
PCIe 7.0 ecosystem support
“Accelerating every interconnect within the data center, including PCI Express, is critical to address the performance demands of AI clusters at scale,” said Debendra Das Sharma, Senior Fellow and Chief I/O Architect at Intel which also develops PCIe silicon. “The combination of Synopsys IP for PCIe 7.0 and Intel’s future generation products will offer system architects both the bandwidth needed for the most demanding data centre workloads and seamless ecosystem integration.”
“To enable deep learning and AI workloads, hyperscalers need reliable, industry-standard interfaces that provide high-performance, low latency connectivity,” said Amin Shokrollahi, CEO at Swiss retimer chip developer Kandou. “With Kandou’s PCIe retimers and Synopsys’ IP, system designers will be enabled with high-bandwidth, secure connections, which are critical for data-intensive, latency-sensitive workloads.”
“PCI Express is at the core of our portfolio of purpose-built connectivity solutions that are used by all major hyperscalers and AI platform providers,” said Casey Morrison, Chief Product Officer at Astera Labs. “PCIe 7.0 is essential to deliver a 2x bandwidth boost at minimal latency which are both critical goals for rapidly evolving Generative AI and high-performance computing applications.”
“PCI Express technology has been essential to the evolution, performance, and interoperability of modern data centre server I/O,” said Rochan Sankar, President and CEO at Enfabrica. “Enfabrica’s Accelerated Compute Fabric silicon can leverage Synopsys’ PCIe 7.0 IP and deliver highly integrated, reliable, and performant scale-up / scale-out interconnect to everyone building next-generation AI compute infrastructure.”
“Data center disaggregation and evolving server architectures need wide ecosystem interoperability to move massive amounts of data efficiently,” said Gerry Fan, CEO at XConn. “XConn’s PCIe/CXL switches and Synopsys’ new PCIe 7.0 IP will be key for these emerging architectures applications, enabling deployment at scale of high-performance, standards-compliant systems.”
“To train large language models, immense volumes of data must be processed faster than ever. PCI Express 7.0 enables scaling high-bandwidth, secure and low latency interconnects to meet tomorrow’s AI data demands,” said Mark Hayter, Founder and Chief Strategy Officer at Rivos. “Rivos RISC-V based AI system solutions with the most advanced interfaces, like Synopsys IP for PCIe 7.0, enable system architects to achieve power efficient, high performance and secure connectivity, critical to deliver the next generation of chips for AI workloads.”
“Microchip is dedicated to advancing high-performance computing and artificial intelligence technologies,” stated Bob Divivier, Appointed Vice President of Microchip’s Data Center Solutions business unit. “Incorporating Synopsys’ advanced PCIe 7.0 IP solution into our next-generation PCIe product line will empower system architects to harness significantly enhanced levels of bandwidth and efficiency in high-level HPC and AI applications.”
“With its high bandwidth and low latency, PCIe 7.0 will provide AI data center infrastructure a dramatic leap in performance,” said Matthew Burns, Global Director, Technical Marketing at connector maker Samtec.
“To help enable the ecosystem and give designers access to early testing, Samtec and Synopsys will demonstrate interoperability testing at PCI-SIG DevCon 2024, showcasing the long-reach performance results of Samtec’s NovaRay I/O panel mount cable system, cable system, and the Synopsys’ PCI Express 7.0 IP,” he said.
If you enjoyed this article, you will like the following ones: don't miss them by subscribing to :
