PCIe 7.0 specification reaches ‘half way point’
The latest version of PCI Express, PCIe 7.0, is on track for launch in 2025 with version 0.5 available today.
PCIe 7.0 updates the standard for PAM4 signalling to achieve 128 GT/s raw bit rate and up to 512 GB/s bi-directionally via x16 configuration while still being backwards compatible. Most leading systems are only now shipping PCIe 5.0 in chips, and PCIe 6.0 was released as a standard at the end of 2021.
The PCIe 7.0 technology is aimed to be a scalable interconnect solution for data-intensive markets including 800G Ethernet, artificial intelligence, machine learning, cloud hyperscaler data centres, high performance computing (HPC) and quantum computing.
The higher performance version of PCIe will also be key for future implementations of the UCIe chiplet interconnect standard.
- End-to-end design and verification for PCIe 6.0
- First PCIe 6.0 and chiplet test chip on 3nm
- Optical PCIe 6.0 technology demonstrated at 64 GT/s
“Progress continues on the PCI Express (PCIe) 7.0 specification, which PCI-SIG announced at US DevCon in June 2022,” said Al Yanes, PCI-SIG President and Chairperson.
“Thanks to the hard work of our technical work groups, we are pleased to announce that version 0.5 is now available for member review. This is the official first draft of the specification, incorporating all the feedback we received from members after the release of Version 0.3 in June 2023.”
The PCIe 7.0 specification remains on track for full release in 2025 using Pulse Amplitude Modulation with 4 levels (PAM4) signaling and focusing on the channel parameters and reach with low-latency and high-reliability. It will also look to improve the power efficiency.
PCI-SIG members can access the PCIe 7.0 specification, version 0.5 on the members workspace.
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