Synopsys supports Intel 18A-P, E process tech
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Synopsys has developed production-ready design flows for the 18A and 18A-P higher performance process technologies at Intel Foundries. These are entering volume production later this year for 1.8nm designs using RibbonFET gate all around (GAA) transistors and the first backside power delivery architectures.
The companies are also working on early design technology co-optimization for the Intel 14A-E efficient lower power process. This is a result of an extensive design technology co-optimization (DTCO) effort between Intel Foundry and Synopsys engineering teams.
Synopsys has also optimised its IP for Intel 18A and expanded support for Intel 18A-P for designs. The Intel 18A process improves performance per watt by 15% over the previous 3nm technology and 30% area improvement. 18-P will boost that performance, while 18-E will increase the density.
- More military customers for Intel 18A
- Intel is sampling Panther Lake processor on 18A
- Aion Silicon joins Intel Foundry Accelerator Design Service Alliance
The AI-enabled EDA reference flow for 18A and 18A-P has a unified exploration-to-signoff platform accelerates 2.5D/3D multi-die designs for Intel’s Embedded Multi-die Interconnect Bridge-T (EMIB-T) chiplet packaging technology.
This can be used in the recently launched Intel Foundry Accelerator Chiplet Alliance as well as the Intel Foundry Accelerator Design Service Alliance.
EMIB-T combines the benefits of EMIB 2.5D and Foveros 3D packaging technologies for high interconnect densities at substrate sizes beyond the reticle limit. The EMIB-T reference flow allows early bump and TSV planning and optimization, with automated UCIe and HBM routing.
“Our production-ready EDA flows, IP, and multi-die solution, provides our mutual customers with comprehensive technologies to accelerate the development of chip designs that meet or exceed their requirements,” said John Koeter, Senior Vice President of the Synopsys IP Group.
“Our continued collaboration with Synopsys enables engineering teams to accelerate ‘systems of chips’ innovation utilizing our unique systems foundry capabilities and optimized Synopsys EDA flows and IP on Intel 18A and Intel 18A-P process nodes to create differentiated designs with faster time-to-results,” said Suk Lee, VP & GM of Ecosystem Technology Office, Intel Foundry.
Synopsys IP and EDA flows are also optimized for power and area on the Intel 18A and Intel 18A-P process nodes to take advantage of the PowerVia backside power using thermal-aware analysis. IP on Intel 18A process node, including 224G Ethernet, PCIe 7.0, UCIe, USB4, embedded memories, logic libraries, IOs, and PVT sensors.
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