MENU

Tackling the chiplet clock challenge

Feature articles |
By Nick Flaherty


The clock network is taking up more and more power as a portion of the chip designs, Vikram Karvat, SVP of Products, Marketing and Planning at Movellus tells eeNews Europe

The company last month raised $23m led by MESH, SK Hynix Intel Captial Candou for its Intelligent Clock Network to tackle the increasing challenges of designing and implementing clock networks. The technology is being used in tapeouts of chip designs from 40nm all the way down to the very latest 3nm chips and chiplet designs, helping with timing closure and also with aging and the long term performance of devices.

“We do have customers at 3nm, but a lot of customers are looking at 5 and 7nm from the mask costs,” he said. “Typically the timing challenge means we are not able to achieve the ideal Vmin as a result of on chip variation, voltage droop, simultaneous switching noise with lots of cores all switching on the same edges and that ripple that that creates noise. But if this is done properly in the clock network you can mitigate the impact of these even for large devices.”

“Architecturally we did two things – you don’t need to synchronise the global clock but at individual modules close to the gates,” he said. “What these modules do is sync the clock between themselves automatically and a clock conductor monitors them with a slow synchronisation clock.

This means the high speed clock is not aligned at the high level and each sync modules takes care of the synchronisation. This completely decouples the clock from the lower levels and makes the timing closure easier to achieve and the size of the system is much greater than with a single synchronous clock domain.

“Now we can also be more sophisticated in compensating for aging as we can adjust at a very granular level with power and frequency control,” said Karvat.

This is more important at smaller process geometries, where the smaller feature size can impact on the long term performance of the chip. The Intelligent Clock IP will be able to compensate for aging effects in the clock.

“A lot of our enhancements are going to be around power, diagnostics including aging so dynamic compensation,” said Karvat. “We have some interesting stuff cooking, the majority for R&D and some for scaling the go to market.

The Maestro platform automates the development of robust clock network solutions with a clock architecture, software automation, and application-optimized IP to solve common clock distribution challenges.

Chiplets

The intelligent clock network IP also provides a key capability for chiplet designs. This allows fully synchronous operation across chiplets, turning 2.5D devices into the equivalent f a large monolithic die.

“There is not clock forwarding, we can implement a die to die interface  and if we get the global clock in there is zero latency from die to die with a fully synchronous design,” said Karvat.

This also helps with the design of a chiplet-based device.   

“You can’t build a full model of a chiplet architecture today as the chip to chip timing can vary, but this allows you to model and validate the entire system with timing closure across chiplets,” he said.

The main chip and chiplets may use a network on chip (NOC) to provide itming but these don’t necessary connect well between devices

“NoCs don’t extend well across chiplets,” he said. “You can either use NOCs on chip and SERDES to go off chip but then you have different NOCs with buffers or you put its all together for a single logical NoC with the clock. For the next year or so for 2.5D designs developers are sticking with what they know, with asynchronous SERDES.”

For 3D chiplets the technology is applied directly, which is why companies such as sk Hynix are interested.

“We were able to close the round with a significant step up in valuation in a challenging economic environment, and SK hynix’s strategic investment is a strong endorsement in our technology and long-term strategy,” said said Mo Faisal, CEO and founder of Movellus

“SK hynix is pushing the envelope on memory performance, and looking beyond process improvements, to system level innovation in 3D packaging and chiplets to maintain the trajectory of the last 50 years,” said Heejin Chung, Head of Venture Investment at SK hynix who joins the board at Movellus. “Movellus’ clock network technology is an avenue to improve not only performance, but we also believe it will improve power and yield for memory and other complex ICs. We’re very excited to enable Movellus to accelerate the adoption of this technology.”

“As companies develop the next generation of complex ICs, new innovations are needed to unlock the power and performance potential of these designs. While the clock distribution network doesn’t get a lot of attention, it is the underlying backbone that orchestrates every chip,” said Edward Chyau, Managing Partner at MESH. “We believe Movellus has the expertise and technology in this field to help companies make dramatic system level improvements, and MESH will leverage its network in the electronics supply chain to support the proliferation of Movellus’ technology.”

www.movellus.com

Other articles on eeNews Europe


Share:

Linked Articles
eeNews Europe
10s