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FPGAs
Microchip AEC-Q100 qualified SoC FPGAs cut power requirements
Microchip AEC-Q100 qualified SoC FPGAs cut power requirements
New Products |
PolarFire System on Chip (SoC) FPGAs from Microchip are now qualified to AEC-Q100 standards set by the Automotive Electronics Council. AEC-Q100…
Everspin and Lattice bring MRAM to FPGA platforms
Everspin and Lattice bring MRAM to FPGA platforms
Business news |
MRAM in FPGA configuration is replacing traditional flash memory in many modern applications such as mission-critical, avionics and automotive.
Exostiv Labs adds support for AMD Versal Adaptive SoCs
Exostiv Labs adds support for AMD Versal Adaptive SoCs
Technology News |
AMD adaptive computing devices enable the design more robust, reliable, and innovative prototypes and SoCs in FPGAs.
SiFive announces 4th generation of RISC-V Essential IP for embedded applications
SiFive announces 4th generation of RISC-V Essential IP for embedded applications
News |
SiFive is seeing growing adoption, with more than two billion SiFive RISC-V based chips already in the market.

Frontgrade Gaisler to design RISC-V processor for space
Frontgrade Gaisler to design RISC-V processor for space
Technology News |
RISC-V processor design to focus on deterministic operation and minimal latency for integration into radiation-hardened MCUs and SoC-FPGAs.
FPGAs target high-performance edge compute
FPGAs target high-performance edge compute
New Products |
FPGAs meet demand for high compute performance and low power in a footprint that can be deployed at the far edge.
QML Class Q qualified FPGAs steamline design
QML Class Q qualified FPGAs steamline design
Business news |
Low power FPGAs bring high levels of density and performance to space applications, saving system cost and engineering efforts.
PolarFire FPGAs verified for single-chip cryptography design flow
PolarFire FPGAs verified for single-chip cryptography design flow
Business news |
Security strength of the FPGAs has been confirmed by the UK National Cyber Security Centre when used with the Single-Chip Crypto Design Flow.


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