TSMC looks to boost European University programme
Europe is at risk of falling behind in leading edge semiconductor design technology says TSMC as it looks to expand its university programme in the region to make leading edge chips.
The programme, launched earlier this year with Belgian research lab imec, aims to support the move from bulk CMOS designs to 16nm and 7nm FinFET technology with multiproject wafers.
“We need to create talent in FinFET designs and get experience to train engineers and designers to work with FinFET technology and contribute designers to the industry,” said Paul de Bot, general manager for Europe at TSMC. “What we see is that many universities are working with bulk technologies.”
The move is not entirely altruistic as having more FinFET designers is crucial for TSMC.
“Half our business comes from advanced technologies at 5nm and 7nm,” he said. “We are offering access to 16 and 7nm PDKs – we started that earlier this year primarily with imec with a big multiport wafer shuttle service as the universities want to publish papers.”
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TSMC is already working with professors and PhD students at Leuven, Munich, Eindhoven, Darmstadt and Montpelier.
“We are welcoming more universities and in Europe we have to step up the activity, as the US and Israel FinFET activity is at a pretty high level but in continental Europe we could do a bit more and universities can help there,” he said.
However leading edge 7nm process technology can take many months to produce with the shuttle service. “We do have a regular schedule for the shuttles and we try to shorten it as much as we can,” he said.
“We are also offering a FinFET design curriculum with a full set of training materials for universities with a design environment,” he said. This includes design tools, although he would not comment on whether TSMC would support open source tools that are more common in university settings.
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