UK startup raises £2.5 million for secure MCU development
SCI Semiconductor Ltd. (Sheffield, England) has raised £2.5 million towards the development of a microcontroller based on CHERI, a memory securing framework.
The funding comes from Mercia Equity Finance and angel investors in the UK and California. The company said it would use the money to set up a base in Sheffield and double its staffby recruiting an additional 20 engineers.
Developed at the University of Cambridge CHERI stands for Capability Hardware Enhanced RISC Instructions and embeds fine-grained memory protection and secure compartmentalization directly into hardware. It protects against cyber-attacks that use software memory misallocation, buffer over flows and other memory hacks. It is suppored by the UK and US governments.
“Memory-safe chips have been shown to prevent 70 percent of all attacks and would enable organisations to continue using existing software,” said SCI CEO Haydn Povey, in a statement.
CHERI goes beyond the use of simple memory address pointers during processing. In addition, the processor expects the address pointer to be accompanied by meta-data that includes permissions and upper and lower bounds for the memory region for the calling function.
SCI is developing a core called Iceni based on Microsoft’s RV32E CHERIoT-Ibex processor that can run “straight” 64-bit RISC-V code or 32-bit CHERI RISC-V code. The first Iceni chip is expected to appear in 2025 and Google Research has signed up as an SCI customer.
SCI Semiconductor was founded in 2023 by Povey and Krishna Anne, who has gone on to become the CEO of Agile Analog (see Agile Analog appoints CEO to drive growth).
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Open source design launched for secure CHERI microcontrollers
First CHERI RISC-V embedded chip and Early Access Programme
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