Verification IP for chiplet designs
Cadence Design Systems has launched 13 Verification IP (VIP) blocks to help engineers using the latest chiplet, high speed bus and memory technologies for data centre chips.
The VIP blocks help the engineers quickly and effectively verify their designs to meet the specifications for the latest standards protocols. These include UCIe universal chiplet interface, the AMBA 5 CHI-f bus and the AMBA Distributed Translation Interface (DTI) as well as the latest version of the DDR5 DIMM memory modules and GDDR7 graphics memories and MIPI A-PHY, SoundWire I3S and USB4 2.0 interfaces.
The blocks have a consistent application programming interface (API) across all VIP with complete bus function models (BFMs), integrated protocol checks and coverage models, helping with rapid adoption.
The MIPI A-PHY 1.1 VIP is also available for automotive chip designers along with VIP for the latest high bandwidth CAN XL bus and ONFI 5.1 flash memory interface.
For consumer and mobile chip designs the same VIP for USB4 2.0, GDDR7, DFI and MIPI SoundWire I3S (SWI3S) is joined by VIP for the latest LPDDR low power DRAM memories and HDMI 2.1 interface.
All the VIP blocks include a specification-compliant verification plan linked to comprehensive coverage models and a test suite to ensure compliance with the interface specification.
The blocks also support the expanded Cadence System-Level Verification IP (System VIP), which provides SoC-level test libraries, performance analysis, and data and cache coherency checkers. Using the expanded System VIP portfolio, customers can experience up to 10X efficiency improvements compared to a manual process for SoC verification.
“The Cadence memory VIP is a critical part of our verification process and instrumental in the successful deployment of our memory PHY IP,” said Ricky Lau, co-founder and CTO of Canadian high speed memory designer The Six Semiconductor.
“Cadence continues to deliver new VIP offerings and advanced SoC verification technologies that support the latest standards. The Cadence VIP offerings have significantly reduced our development time and increased the confidence of our customers,” he said.
“As requirements evolve and demand increases for higher bandwidth, lower power and more effective cache coherency management, new protocols arrive to address these issues,” said Paul Cunningham, senior vice president and general manager of the System & Verification Group at Cadence.
“With these 13 new VIP, Cadence is offering customers solutions to ensure the designs comply with the standard specifications as well as application-specific timing, power and performance metrics, providing the fastest path to IP and SoC verification closure.”
The VIP blocks are part of the broader Cadence verification full flow, which includes Palladium Z2 emulation, Protium X2 prototyping, Xcelium simulation, the Jasper Formal Verification Platform, the Helium Virtual and Hybrid Studio, and the Verisium AI-Driven Verification Platform.
www.cadence.com/go/NewVIP2023.
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