ARM pushes chiplets and 3D packaging for Neoverse chips

April 27, 2021 // By Nick Flaherty
ARM pushes chiplets and 3D packaging for Neoverse chips
ARM's CMN-700 interconnect IP will support up to 128 Neoverse cores on a chip

ARM has launched an enhanced mesh interconnect IP for its high performance Neoverse processor cores that enables more use of chiplets and 3D packaging.

Chiplets allows separate chips to be used in the same package to provide high speed data links or stacked memory. The CMN-700 supports 144 end points for 128 cores plus chiplets and memories, rather than the limit of 64 for the previous CMN-600. 

“CMN-700 [is] a key element for constructing high-performance Neoverse V1 and Neoverse N2-based SoCs,” said Chris Bergey, SVP and GM, Infrastructure Line of Business at ARM. “Platform IP is essential which is why we developed the CMN700 mesh interconnect  with DDR5 support and multichip capabilities,” he said. “It adds CXL to build host or end point devices and the the other key multichip upgrade was for multi-die and chiplet integration and this will open new doors and allow more flexibility,” he said.

The mesh interconnect is intended to support scaling of cores to provide more performance, rather than running multiple threads in each core. This is key to the power consumption and security, says Berger. “We think Neoverse dedicated cores offers a better approach with more predictable performance and more immune to side channel attacks instead of shared threads,” he said.

The previous N1 chip supported 64 cores with CMN-600, and the new interconnect IP will allow the first N2 chips to have 80 cores available with versions planned with 128 cores. The Neoverse V1 chips will have up to 96 cores, said Gerber.

Marvell is using the Neoverse N2 for its next generation of OCTEON data centre chip that will begin sampling by end of 2021, providing a 3x performance over the previous parts.

Related Neoverse articles  

Picture: 
The CMN-700 interconnect for Neoverse V1 and N2 datacentre chip designs

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