ARMv9 looks to a decade of AI chips

March 30, 2021 // By Nick Flaherty
ARMv9 looks to a decade of AI
ARM has released initial details of its ARMv9 instruction set architecture (ISA) that will add artificial intelligence and more security to CPUs, GPUs and dedicated accelerators for the next decade of chip designs.

Partner of Cambridge-based ARM have shipped 180bn devices since 1991 but the company expects over 300bn to ship in the next ten years, driven by its ARMv9 architecture.

However the actual details on the implementation of ARMv9 microarchitecure are scarce, even though the first A-class chips will be sampling by the end of the year. These will be aimed at mobile handsets and data centre chips.

One challenge is bringing the scalable vector extensions (SVE) that are used in the Fugaku ARM-based supercomputer into the A-class chips for AI in mobile phones and also into the R-class real time controllers and M-class microcontrollers.

“We’ve been working on v9 for so long its great to bring it out to public,” said Simon Seagars, CEO of ARM. “There is a particular focus on the execution of ML workloads and DSP, but the main centre of attention is the eco-system, allowing them to write code and have it work across any platform with the right level of standardisation is important.”

The ARMv9 SVE2 extensions add the ability to compress and decompress code and data inside the CPU core to reduce off chip data movement and so reduce the energy consumption. “SVE2 is a pretty major step, it expands the sizes of data types we can operate on and will drive a significant performance uptick on many applications,” said Seagars.

“Reusing data is something we’ve been looking at for years – moving data on and off chip is very power hungry so we have done lots of things over the years to use data on the chip. That’s why we have increased the data size in SVE2. The more data you can hold on the chip the better the energy efficiency.”

However SVE2 will have to be tweaked for the R-class and M-class implementations he says. This will be competing more directly with extensions in the RISC-V architecture.

Another aspect of the ARMv9 ISA is a security feature called realms. This brings the security enclaves used by companies such as NXP for the i.MX9 and Lattice Semiconductor to mainstream chips. The realms are dynamic safe areas to store data and execute code separate from the privilege mode of the operating system or a hypervisor.

This builds on ARM’s TrustZone technology and is a hardware version of software containers that allows applications to run easily across different systems. However this will require changes to operating systems such as the Linaro version of Linux and to hypervisors, hence the focus on the eco-system.

“We see no reason why Realms cannot provide security in the highest performance systems, from the cloud and data centre and supercomputers all the way down,” said Seagars. “Realms is a new technique that we anticipate will be widely used and we are working very hard on the software side to help people build the software that sits on top of the hardware.”

ARMv9 is aiming to address AI and security from sesros all the way to the data centre servers

The company plans the same yearly cadence for releases of the ARMv9 architecture. “With ARMv8 we created additional profiles for R and M that implemented features in slightly different ways and I expect that to be a similar path for v9,” said Seagars. “We are not announcing a schedule for R and M but over time those will roll out in implementations of our CPUs.”

The company also wants to provide a standardisation process which it calls SystemReady so that code can easily run across any v9 processor. This has to take into account a multitude of different CPU, GPU and eural network NPU cores as well as peripherals.

“We have architectural models that software developers can use to work out how the technology works and we are also working with tool makers,” said Seagars. “Then there are activities such as SystemReady that help with the standardisation.”

The main focus on standardisation, security and code portability is on the data centre where Amazon is a key customer with its Graviton chips. “We expect Neoverse cores on v9 out in the market in the not too distant future,” said Seagars. “We see a lot of activity around the ARM architecture in the data centre and we are expecting other data centre vendors to be deploying ARM technology and over time there will be a shift from v8 to v9,” he said.

“As we look at the next ten years of compute there is no one size fits all. From the wider set of execution units to handle those vectors down to tiny energy efficient microcontrollers that don’t have huge processing but still have to do it in the most energy efficient and secure way so we want to mix and match these capabilities of the CPU, GPU, NPU and any other processing in a framework with as much reuse as possible,” said Seagars.

www.arm.com

Related articles 

Other articles on eeNews Europe 

Picture: 
Simon Seagars, CEO of ARM

Vous êtes certain ?

Si vous désactivez les cookies, vous ne pouvez plus naviguer sur le site.

Vous allez être rediriger vers Google.