The European Processor Initiative is aiming to have a combined ARM and RISC-V chip for high performance computing (HPC) in 2022, a year later than originally planned.
The EPI has 27 partners from 10 European countries with the goal of helping the EU achieve independence in HPC technologies and says it has stayed on track despite the cancellation of its first European Processor Initiative Forum.
The project partners have finalized the first version of its RISC-V accelerator architecture, named EPAC, and expects test chips next year towards the end of its three-year project. The EPAC Test Chip silicon, codenamed Titan, will be complemented with a PCIe EPAC Test Platform enabling the test and enhancements of the architecture for future revisions and to build prototype systems.
The project aims to produce a multicore device, codenamed Rhea, using both ARM Zues and the RISC-V cores on TSMC's 6nm process by 2022, although the orignal timeline had this planned for 2021. A second generation device codenamed Cronos will combine the include the EPAC accelerator alongside the ARM Neoverse V1 high performance data centre core. This will be the main engine for building a European exascale supercomputer in 2023.
RISC-V pioneer SiPearl has been a key player, SiPearl signed a licensing agreement with Arm and opening a branch in Germany. Competitor SiFive is also working with the Supercomputer Centre in Barcelona, and EPI partner, on the RSIC-V technology for an exascale supercomputer.
"SiFive is very interested in exascale computing and we are working with BCS Barcelona using a simulation framework for a full system model and adding to the RISC-V standard for vector processor to make exascle processing even more powerful," said Nasr Ullah , senior director of performance archiecture at SiFive
The EPI project already has a compiler supporting RISC-V vector intrinsics and automatic parallelization of C/C++ codes and is evaluating the generated code on emulation