Cadence moves verification IP up to the chip level: Page 2 of 2

October 14, 2020 // By Nick Flaherty
Cadence moves verification IP up to the chip level
System-Level Verification IP (System VIP) is a suite of tools and libraries from Cadence Design Systems for automating full system-on-chip (SoC) design testing

I/O peripherals,” said Tran Nguyen, director of Design Services at Arm. “By using Cadence System Traffic Libraries and System Performance Analyzers, Arm was able to automate complex test generation processes, enabling a quicker PCIe integration verification and performance analysis.”

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