Codasip, Imperas team for RISC-V processor IP verification

November 24, 2021 // By Nick Flaherty
Codasip, Imperas team for RISC-V processor IP verification
Codasip has included golden reference models from Imperas in its DV testbenches to ensure an efficient verification flow

RISC-V core developer Codasip has adopted reference designs and verification tools from Imperas Software for its IP.

Codasip has invested heavily into processor verification to deliver the industry’s highest quality RISC-V processors and has included Imperas golden reference models in its DV testbenches to ensure an efficient verification flow that accommodates a wide range of flexible features and options while scaling across the entire roadmap of future cores to enable rigorous confirmation of functional quality.

The open source RISC-V instruction set offers many different permutations of base instructions, standard optional extensions and custom instructions, raising concerns about implementations and the risk of fragmentation. Codasip’s internal testing already uses an internal instruction-accurate model, several sources of direct and random testing (internal and externally provided), and several different technologies to check and ensure processor compliance. Imperas configurable reference models are already fully tested and enable all the configuration options needed to support this comprehensive view.

The Codasip engineering team based in Sophia-Antipolis, France, reviewed the evolving RISC-V specifications, the full Codasip processor IP portfolio, extensions and configurable features, plus future roadmap plans. They set up test frameworks around the Imperas RISC-V Reference Models to efficiently test all configurations with the ability to adapt for new roadmap features.

“Imperas are the pioneers in simulation technology and processor verification for RISC-V,” said Philippe Luc, Verification Director Codasip. “While processor verification is not a new problem, there are many RISC-V suppliers, with customization and various levels of verification or conformance: customers are legitimately concerned about both quality and fragmentation. Codasip is very proud of our rigorous approach to verification– using Imperas as an important part of our quality process furthers extend our differentiation. The Imperas independence, reputation and technical strength provides our customers with further reassurance in our ‘best in class’ RISC-V processors.”

“Codasip provides the RISC-V market with a range of processor solutions that enable optimized performance for a wide range of applications. Design verification of this processor IP is fundamental to Codasip continuing to deliver the highest-quality processors as it moves to the next generation of its IP. Each additional optional feature roughly doubles the verification workload,” said Simon Davidmann, CEO at Imperas Software. “The Imperas approach supports Codasip’s development by applying Continuous Integration/Continuous Development to a sophisticated processor DV environment by using simulation and offers an efficiency advantage without compromising optional features. Imperas and Codasip share a common vision that improved quality is essential to the success of RISC-V.”

The Imperas RISC-V Reference Models for Codasip are available now to lead customers and partners for software development and as a foundation for virtual platforms.

www.codasip.com; www.imperas.com

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