French design house Allegro DVT has developed the first hardware decoder IP for the latest Versatile Video Coding (VVC, H.266) video standard.
The AL-D320 core supports 8, 10 and 12-bit samples, chroma sampling of 4:2:0 and 4:2:2 and image resolutions and rates of up to 8K120. Added to this, the core continues to support H.264 and HEVC up to 12-bit and 4:4:4 chroma subsampling.
The VVC/H.266 format aims to provide 30-50 percent better video compression for the same perceptual video quality as H.265, and supports resolutions up to 16K as well as 360° videos.
“The increased complexity of VVC requires HW based implementations for the decoding function to achieve the best trade-off between power consumption, performance and total cost of the solution,” said Nouar Hamze, CEO of Allegro DVT.
“The increase in complexity of leading-edge video codecs has lengthened development time. We have developed and released our VVC decoder IP early on to accelerate market adoption. Our release pre-empts the demand in a way that we believe will enable OEMs and semiconductor vendors to confidently move forward with the introduction of solutions with VVC decoding capability and therefore speed up the adoption of this new codec to unlock new use cases such as 8K broadcast worldwide,” he said.
The AL-D320 employs a unique multi-format and multi-core architecture which allows scalability to seamlessly support additional video codecs such as AV1/VP9/HEVC/H.264 and higher decoding throughputs up to 8K60 and 8K120.
The AL-D320 decoder IP core also provides ultra-low latency decoding down to sub-frame for all mainstream video formats: VVC, AV1, VP9, H.265/HEVC and H.264/AVC, and higher decoding throughputs up to 8K120. In addition, chroma sampling of up to 4:4:4 and sample size up to 12-bit are supported.
The AL-D320 builds on existing production-proven video decoder semiconductor IP cores to provide both early access to the latest technology while at the same time minimizing adoption risk. It supports the AMBA APB interface for control registers programming and AMBA AXI interfaces for data access.
Deliverables include RTL source code, C control software, a bit accurate executable software reference model and documentation
The AL-D320 decoder IP is immediately available for integration by SoC vendors in various technology nodes ranging from 28nm down to 5nm and below through a seamless and proven HW and SW integration kit.
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