Samsung Foundry tapes out 3nm GAA chip
Taking on TSMC at the leading edge of process technology, Samsung Foundry has taped out a 3nm chip that uses its Gate-all-around (GAA) transistor architecture.
This requires a different set of design and qualification tools from the FinFET transistor structures used by TSMC and Intel, so Samsung used the Fusion Design Platform from Synopsys. The physical design kit (PDK) for the process was released in May 2019 and tools were qualified on the process last year.
The tapeout was the culmination of an extensive collaboration between Synopsys and Samsung Foundry to accelerate the delivery of a highly optimized reference methodology for the GAA process.
The reference design flow includes an integrated and golden-signoff-enabled RTL-to-GDSII design flow coupled with golden-signoff products. The flow is aimed at customers wanting to use the 3nm GAA process for chips in high-performance computing (HPC), 5G, mobile and advanced, artificial intelligence (AI) applications.
- Samsung releases PDK for 3nm gate-all-around process
- Samsung 3nm designs can start on Cadence EDA tools
“Samsung Foundry is at the heart of fueling the next phase of industry innovation with our continued process-technology-based evolutions to meet the growing demands of both specialized and broad-market applications,” said Sangyun Kim, Vice President of Foundry Design Technology Team at Samsung Electronics. “Our latest, advanced 3nm GAA process has benefited from our extensive collaboration with Synopsys, and the accelerated readiness of the Fusion Design Platform to enable the efficient realization of the 3nm process’ promise, is a testament to the importance and benefit of these key alliances.”
The GAA architecture has improved electrostatic properties that translate to increased performance and reduced power with the added benefit of new optimization opportunities based on the additional vector of nano-sheet-width control, says Samsung. Used with well-established voltage-threshold tuning, this provides more ways to optimise the design for power, performance or area (PPA).
The design flow also includes support for complex placement methodologies and floorplan rules, new routing rules and increased variability. The flow is based on a single data model and uses a common optimization architecture, rather than combining point tools.
“The GAA transistor structure marks a key inflection point in process-technology advancement that is critical in maintaining the scaling trajectories needed for the next wave of hyperscale innovation,” said Shankar Krishnamoorthy, general manager of the Digital Design Group at Synopsys. “Our strategic collaborations with Samsung Foundry in support of the co-delivery of best-in-class technologies and solutions are ensuring the continuation of these scaling trends and the associated opportunities these offer to the broader semiconductor industry.”
Synopsys technology files are available from Samsung Foundry for the 3nm GAA technology process.
The Fusion Design Platform includes Fusion Compiler, IC Compiler II place-and-route and Design Compiler RTL-synthesis for digital design, PrimeTime timing signoff, StarRC extraction signoff, IC Validator physical signoff and SiliconSmart library characterization.
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