The N3 3nm node at TSCM enters ‘risk production’ by the end of this year with volume production in 2022. This is likely to be the last process generation to use FinFet transistors as the industry looks to 2nm designs.
“We're pleased with the result of collaboration with Arm in delivering Arm cores with POP IP on TSMC's advanced process,” said Suk Lee, vice president of the Design Infrastructure Management Division at TSMC. “This helps our mutual customers achieve silicon innovations benefitting from the significant power and performance boost of our 3nm technology and quickly launch their new product innovations to market.”
ARMv9 SoCs are expected to have multiple CPU cores with complex interconnect and power management strategies, implementing standards such as AMBA CHI. This complexity inherently comes with challenges that need to be well understood for optimal implementation in 3nm technology.
The aim is to optimize the critical paths for physical IP, says Kiran Burli, senior director of marketing for the Physical Design Group at ARM. Custom recipes and tight collaboration with electronic design automation (EDA) vendors improves the timing correlation between placement and final routing.
Ultimately, there is a trade-off between hitting the target performance, managing power, and electromigration with a robust power grid. Logic and power grid optimization are essential for minimal voltage droop, timing, and routing congestion.
The ARM physical IP is designed for high and low voltage tolerance, logic libraries with high-drive cells, technology files supporting aggressive via pillars or ladders, as well as high sigma timing sign-off using LVF – all of which are included in POP IP implementations for Armv9 Cortex and Neoverse cores, says Burli.
The company has been working with Synopsys, Cadence Design Systems and Siemens EDA to qualify the design tools on the TSMC 3nm process.
The 3nm ARMv9 POP IPs and the underlying ARM Artisan Physical IP are developed in close collaboration with the ARM processor development teams in an iterative process that identifies optimal performance and energy efficiency. French chip designer SiPearl is using the physical IP for its supercomputer chip based on the Neoverse processor design.
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