French chip designer SiPearl has teamed with Open-Silicon Research (OSR) in India to develop a 6nm ARM chip for embedded high performance computing (HPC) in 2.5D packaging.
The chip, called Rhea, will be based on 64 ARM cores with over 30bn transistors and will be built on TSMC’s 6nm process. This will use the Value Chain Aggregator (VCA) programme through OSR’s US parent company, OpenFive, which is the open IP subsidiary of RISC-V chip developer SiFive. SiPearl already has a license from ARM to use the Neoverse V1 core, codenamed Zeus, and will use this for Rhea.
The SoC design will also use some RISC-V elements along with OSR’s High Bandwidth Memory (HBM2E) IP subsystem, die-to-die (D2D) interconnect and HBM memory die in a single 2.5D advanced package. However, the SoC is expected to ship in Q4, 2022, so there is a long way to go with the design and integration.
The multi-year joint collaboration with OSR will expand the range of HPC designs, using OSR’s deep-submicron physical design implementation, advanced 2.5D packaging and global supply chain management.
The SoC is aimed at HPC applications using artificial intelligence (AI) such as autonomous driving, facial recognition and genomics that generate vast amounts of data.
Open-Silicon Research will also contribute leading-edge deep-submicron physical design methodology that will make it possible to efficiently implement the 6nm SoC die with advanced 2.5D packaging expertise to manage the very high thermal dissipation, and supply chain experience to ensure a smooth ramp up to volume production.
“We highly regard our partnership with Open-Silicon Research, and we’re excited to utilize the company’s experience implementing very large deep-submicron custom silicon designs, together with their global supply chain management track record shipping production volumes, to deliver this highly complex 6nm SoC solution with differentiated HBM2E IP in a highly advanced 2.5D package,” said Philippe Notton, Founder of SiPearl. “We are confident that this partnership will