Ethernet field buses have been used for decades for real-time and deterministic data transmission for control and automation purposes. The problem: they are all manufacturer-specific - whoever uses them is trapped in the respective ecosystem. TSN as a standard protocol could gradually replace these real-time-capable fieldbus systems, because it brings together the different types of data traffic with different requirements in one network. "Not only do the network's data traffic requirements vary, but also the topologies and the devices used in the network," explains Marcus Pietzsch, group leader IP Core and ASIC Design at Fraunhofer IPMS .
To meet the different requirements, the Fraunhofer developers have developed three different TSN IP cores. The TSN-EP is intended for the implementation of end devices such as sensors or actuators in an Ethernet network. The TSN-SE is intended for switched endpoints and can be used for end devices in daisy-chain topologies. The TSN-SW, the latest development, is suitable for multiport switches with or without integrated endpoint functions.
The platform-independent Time Sensitive Networking IP core designs developed by Fraunhofer IPMS facilitate the integration of TSN in devices to be used in an Ethernet TSN network and are optimised for lowest latencies. The IP cores are silicon proven for ASIC technologies up to 22nm. In addition, they can be implemented in FPGAs from various manufacturers.
The multidisciplinary IP design team of the Fraunhofer IPMS with expertise in domain-specific computer architectures, RTL design and the implementation of electronic systems is also available as a competent development partner for application-specific adaptations of the IP cores and their integration into complex network architectures.
Fraunhofer will present the new TSN Switch IP-Cores at the TSN/A Conference from October 7th to 8th, 2020.
More information: https://www.ipms.fraunhofer.de/en.html