Research lab imec in Belgium has shown working versions of a transistor structure that could be used for 2nm and 1nm chip designs
The forksheet devices have a short-channel control (SSSAT=66-68mV/dec) comparable to gate-all-around (GAA) nanosheet devices down to 22nm gate length. Dual work function metal gates are integrated at 17nm spacing between n- and pFETs, highlighting the key benefit of forksheet devices for advanced CMOS area scaling.
Unlike nanosheet devices, the forksheets are controlled by a tri-gate forked structure that has a dielectric wall in between the p- and nMOS devices before gate patterning. This wall physically isolates the p-gate trench from the n-gate trench, allowing a much tighter n-to-p spacing than what is possible with either FinFET or nanosheet devices.
Simulations in 2019 showed this approach had better area and performance scaling to 2nm and 1nm than GAA devices as a result of the reduced Miller capacitance that comes from a smaller gate-drain overlap.
This is not just an R&D lab-based development, as the forksheet devices were successfully integrated by using a 300mm process flow, with gate lengths down to 22nm. Both n- and pFETs, each with two stacked Si channels, were found to be fully functional. The short channel control of 66 to 68mV is comparable to that of vertically stacked nanosheet devices that were co-integrated on the same wafer for a direct comparison that was detailed at the VLSI 2021 Symposium this week.
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For the forksheet devices, dual work function metal gates were integrated using a replacement metal gate flow at an n-p space as tight as 17nm (which is about 35 percent of the spacing in state-of-the-art FinFET technology), highlighting one of the key benefits of the forksheet architecture.
“From 2022 onwards, it is expected that today’s leading-edge FinFET transistors will gradually give way to vertically stacked nanosheet transistors in high-volume manufacturing, as the FinFET fails to provide enough performance at scaled dimensions,” said Naoto Horiguchi, Director CMOS Device Technology at imec.
“Process limitations will however pose a limit to how close the nanosheet’s n and p devices can be brought together, challenging further cell height reduction. The new forksheet device architecture – which is a natural evolution of the GAA nanosheet device – promises to push this limit, allowing track height scaling from 5T to 4.3T while still offering a performance gain. Alternatively, with a forksheet design, the available space can be used to increase the sheet width and as such further enhance the drive current. Our electrical characterization results confirm that the forksheet is the most promising device architecture to extend the logic and SRAM scaling roadmaps beyond 2nm leveraging the nanosheet integration in a non-disruptive way."
The leading edge of the semiconductor industry is moving to 3nm later this year with early production, and mass production in 2022. This puts the need for 2nm process technology in 2023 for risk production and mass production by the end of 2024 or early 2025.
"After the forksheet, we are anticipating complementary FETs (CFETs) to enter the logic scaling roadmap,” said Horiguchi. "These transitions will allow us to gradually push track height scaling of standard cells below 4T, while still providing a power-performance advantage. Beyond CFETs, 2D monolayer crystalline materials like tungsten disulfide (WS2) are promising replacements for Si in CMOS channels, offering opportunities for further gate-length scaling.”
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