Siemens EDA uses 2.5D packaging to boost verification system to 15bn gates

March 26, 2021 // By Nick Flaherty
2.5D packaging boosts hardware-assisted verification system
The Veloce Hycon emulation system from Siemens Digital Industries Software combines a virtual platform, hardware emulation, and FPGA prototyping to accelerate hardware and software verification

Siemens Digital Industries Software has launched the next generation of its Veloce hardware-assisted verification system with a key use of 2.5 packaging to boost capacity.

The Veloce HYCON (HYbrid CONfigurable) system combines a virtual platform, hardware emulation and Field Programmable Gate Array (FPGA) prototyping technologies for the development of leading edge system-on-chip designs.

Developers can use their own virtual SoC models early in the cycle on a range of processors that has been expanded to include the AMD EPYC 7003 series. They can then begin running real-world firmware and software on Veloce Strato+ to provide visibility down to the lowest level of hardware, with an upgrade to allow two virtual users at the same time.

The key is that developers can then move the same design to Veloce Primo to validate the software/hardware interfaces and execute application-level software while running closer to actual system speeds. To make this approach as efficient as possible, Veloce Strato+ and Veloce Primo use the same RTL, the same virtual verification environment, the same transactors and models to maximize the reuse of verification collateral, environment and test content.

Veloce Strato+ is a capacity and capability upgrade to the Veloce Strato hardware emulator, now supporting up to 15 billion gates. This is based on Crystal 3+ package that provides 1.5x the capacity for emulation using a 2.5D approach that combines multiple die in one package.

Strato+ uses the same 28nm proprietary chip from the second generation system launched in 2017 by Mentor Graphics with the same chassis that holds 64 boards. Moving the memory into the package as die reduces the complexity of the board (which Siemens calls the AVB) and allows more chips per board, up from 16 to 24. This allows each chassis to emulate 3.3bn gates.

“In 2017 we said Strato was the path to 15bn gates, one chassis is 2.5bn gates with four in a frame to provide 10bn gates of capacity with 16 chips on 64 boards,” said Jean-Marie Brunet, Senior Director of Product Management and Engineering for the Scalable Verification Solutions Division at Siemens EDA.

"We kept the logic die intact and moved the memory components used for trace into a 2.5D package and as a result you have more free space on the board and 24 chips, giving 15billion gates,“ he said.

"The die is still at 28nm – that is still the most effective process for performance and price as it is the last silicon process that is single mask without double patterning. This is a risk reduction for our customers,“ he told eeNews Europe. "The feedback from AMD says it’s a push button change, the behaviour is the same as it’s the same die,“ he added.

The increase in power consumption has also been addressed. The second generation chassis required 50kW, but the Strato+ is sees an increase of 20 to 22 percent more in power, says Brunet. "By increasing the capacity the efficiency is higher, the W/MG is lower and that’s what customers want,“ he said.

For prototyping, Veloce Primo is an internally developed modular FPGA prototyping system based around Xilinx FPGAs that scales up to 320 devices.“Xilinx has a long-standing relationship with Siemens both as a customer and as a collaboration partner, and we’re excited to provide our recent and industry-leading Virtex UltraScale+ VU19P device enabling scalability and capacity to this new product offering,” said Hanneke Krekels, senior director, Core Vertical Markets at Xilinx.

“As we enter the new semiconductor mega-cycle, the era of software-centric SoC design requires a dramatic change in functional verification systems to address new requirements,” said Ravi Subramanian, Senior Vice President and General Manager, Siemens EDA.

“The introduction of the next-generation Veloce system that addresses these key new requirements is a direct result of the focused investment from Siemens to offer our customers a complete, integrated system with a clear roadmap for the next decade. With today’s announcement, we are establishing a new standard for a system that is capable of supporting the new verification requirements across a diverse set of industries-spanning computing and storage, AI/ML, 5G, networking, and automotive.”

AMD has been the lead partner for the development. “AMD uses Veloce Emulation platforms as part of our pre-silicon verification and validation solutions,” said Alex Starr, corporate fellow, Methodology Architect at AMD. “The high-performance designs we create demand scalable, dependable and innovative emulation solutions. We’re excited to see 2nd and 3rd Gen AMD EPYC processors qualified for use with Veloce Strato and Veloce Strato+ platforms.”

The consistent working model with Veloce Strato+ in terms of software workloads, design models and front-end compilation technology reduces the cost of verification by using the right tool for the task where the emulation and the prototyping work together as complimentary solutions for a better outcome in the shortest cycle. Veloce Primo also supports both virtual (emulation offload) and in-circuit-emulation (ICE) use models for highest possible performance while maintaining accurate clock ratios in both modes.

“The increasing demand for computing in all industries means time to market is critical,” said Tran Nguyen, senior director of design services ar ARM. “The Veloce Primo enterprise FPGA prototyping solution from Siemens helps Arm quickly resolve design issues and achieve verification objectives so that our ecosystem can deliver quality Arm-based SoCs to support the rapid pace of innovation.”

The Hycon system extends to the desktop with Veloce proFPGA through an OEM agreement with Pro Design. This scales from 40M gates to 800M gates based on high-end FPGAs including Intel Stratix 10 GX 10M and Virtex UltraScale+ VU19P device.

“The advanced technology found in the proFPGA family delivers many advantages for validating today’s AI/ML, 5G, and data centre ASIC designs,” said Gunnar Scholl, CEO of Pro Design. “We are excited to partner with Siemens. Our collective experience, insight and strategy for the FPGA desktop prototyping market is being recognized, and we are excited to accelerate market penetration in this space through the collaboration with Siemens.”

The full Veloce Hardware-Assisted Verification system is now available and in production use at lead customers worldwide.

https://eda.sw.siemens.com/en-US/ic/veloce/

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