Power integrity for waferscale AI with 400,000 cores: Page 2 of 2

August 28, 2020 // By Nick Flaherty
Chief hardware architect Sean Lie of Cerebra
A waferscale AI processor from Cerebra Systems is using a power integrity monitor from Analog Bits that is being ported to 5nm and 3nm processes

cascadable with up to 5 macros off the same power supply and there is independent programming for different glitch levels between 0.675 to 0.935 voltage with a trigger value of ± 10mV with 5pV sensitivity. There is no clock but the outputs are latched to make it easier to integrate the macro into the system.

“The silicon is proven in the 7nm 7FF process and is being ported to N5 which will be available in Q3 2020,” said Tirupattur. “This macro will be available in N3 in the first quarter of 2021.

“We are also working on a system power supply in N5,” he added. “The difference is that it has a programmable droop detection as well to program the system power. This will be available in Q3 2020 and we have an N7 test chip that is undergoing characterisation.”

Cerebras is planning to build its second generation system on TSMC’s N7 7nm process. This is set to have 850,000 cores with 2.6tn transistors.

The current waferscale system is packaged as the CS-1 and is fully programmable. It installs in a standard rack in a data centre and has the performance of a large cluster of GPUs with the programming benefits of a single node.

The engine is being integated with the US National Nuclear Security Administration’s (NNSA) 23-petaflop Lassen supercomputer at the Lawrence Livermore National Laboratory (LLNL).


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