Samsung looks to 2nm in 2025

October 06, 2021 // By Nick Flaherty
Samsung looks to 2nm in 2025
Samsung is planning to have 2nm process technology in production in 2025 following its 3nm process in mass production next year.

Designs are already starting using the 3nm Gate-All-Around (GAA) Multi-Bridge-Channel FET transistor structure. This MBCFET will drive a 35 percent decrease in area, 30 percent higher performance or 50 percent lower power consumption compared to the 5nm process. The yield is already approaching that of the 4nm process that is in mass production says the company.

“We will increase our overall production capacity and lead the most advanced technologies while taking silicon scaling a step further and continuing technological innovation by application,” said Dr. Siyoung Choi, President and Head of Foundry Business at Samsung Electronics speaking at the 5th annual Samsung Foundry Forum (SFF) 2021. “We expect the transition to 2nm to be smooth, given the experience with 3nm.”

An announcement on the location for a new fab in the US is coming soon, says Choi.

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Samsung is scheduled to start producing its customers’ first 3nm-based chip designs in the first half of 2022, while its second generation of 3nm is expected in 2023. The 2nm process node with MBCFET is in the early stages of development with mass production in 2025.

However Samsung Foundry is still improving its current FinFET process technology to support specialty products with cost-effective and application-specific competitiveness. The 17nm FinFET provides up to 43 percent decrease in area, 39 percent higher performance or a 49 percent increase in power efficiency compared to the 28nm process.

 It is also developing its 14nm process for 3.3V high voltage or flash-type embedded MRAM (eMRAM) which enables increased write speed and density in microcontrollers (MCUs), IoT and wearables. The shift from the 14nm radio frequency (RF) platform to 8nm is expected to be popular for the 5G semiconductor market from sub-6GHz to mmWave applications.

It is also looking at more use of 3D and chiplet technologies for heterogenous integration of RF and digital devices in a single package.

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