Streaming Scan Network cuts test cost for large system-on-chip designs

November 04, 2020 // By Nick Flaherty
Streaming Scan Network cuts test cost for large system-on-chip designs
Samsung Foundry has included the Tessent Streaming Scan Network test system from Mentor in its leading edge reference flow to cut test time by a factor of four.

Mentor, part of Siemens, has developed a bus-based scan data distribution architecture that enables simultaneous testing of any number of cores. This helps shorten test time by enabling high-speed data distribution, efficiently handling imbalances between cores and supporting testing of any number of identical cores in a large system-on-chip design with a constant cost. It also provides a plug-and-play interface in each core that simplifies scan timing closure and is well-suited for abutted tiles.

The software includes embedded infrastructure and automation that decouples core-level DFT requirements from the chip-level test delivery resources. This enables a no-compromise, bottom-up DFT flow that can dramatically simplify DFT planning and implementation, while reducing test time by a factor of four. Mentor developed the technology in collaboration with multiple leading semiconductor manufacturers and is part of the reference flow for Samsung Foundry.

Growing demand for next-generation integrated circuits (ICs) that deliver the extreme performance required for fast-evolving applications such as artificial intelligence and autonomous driving has resulted in an unprecedented increase in the size of IC designs, which today can integrate many billions of transistors. Larger IC design sizes and associated complexity translate to a dramatic rise in the time and cost required to test these massive IC designs, as well as the engineering effort needed to plan for and deploy design-for-test (DFT) structures and functionalities across each design.

The Tessent Streaming Scan Network software is part of the TestKompress software and has full support for tiled designs and optimization for identical cores, so it suitable for increasingly large emerging compute architectures.

“The dramatic spike in IC test complexity due to increasing design sizes, advanced technology nodes, and use-model requirements presents significant challenges for IC design organizations,” said Brady Benware, vice president and general manager of Tessent Silicon Lifecycle Solutions for Mentor, a Siemens business. “With the Tessent Streaming Scan Network, our customers can be ready for the designs of tomorrow, while

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The Tessent Streaming Scan Network from Mentor cuts test time by a factor of four.

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