Senior managers from TSMC in Taiwan and Europe have been highlighting the fact that the company does not compete with its customers.
“We do not compete with you, we are a pureplay foundry,” said Maria Marced, president of Europe at the TSMC technology symposium today.
The move comes as the company prepares for early production of its 3nm process technology later this year and mass production in the second half of 2022. The company would not comment on its schedule for its 2nm process technology.
“We will never have our own products to compete with yours,” said CC Wei, CEO of TSMC at the same event. He also emphasised the previously announced $100bn investment in capacity to reassure customers about the current shortages.
The company is launching a 5nm process for automotive designs alongside a variant for RF chips. It is also expanding its 3D packaging capability that currently fills five dedicated fabs in Taiwan.
“We have extended N5 to automotive on N5A to support the demand for AI-enabled driver assistance and the digitization of vehicle cockpits. N5A combines the high volume 5nm process with the reliability requirements of AEC-Q100 Grade 2 as well as other automotive safety and quality standards,” said Wei.
N5A is scheduled to be available in third quarter of 2022.
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An optical shrink of the 5nm process is due for early production later this year. N4 provides a 6 percent density improvement with compatible design rules to N5 as well as a reduction in the number of masks to cut costs. Risk production is set for the third quarter of 2021.
For 5G smartphones, TSMC showed the N6RF process, which brings the power, performance, and area benefits of the 6nm logic process to 5G radio frequency (RF), sub 6GHz and millimetre wave chips as well as WiFi 6/6e designs. This is aimed at designs currently on a 16nm process and would boost the cut off frequency up from 257GHz in 16FFC to 310GHz with a 40 percent power reduction
For high-performance computing applications, particularly from Intel competitor AMD, TSMC will be offering larger reticle-size for both its InFO_oS and CoWoS packaging technology later this year. This will enable larger floor plans for chiplet and high-bandwidth memory integration. Additionally, the chip-on-wafer (CoW) version of TSMC-SoI™ will be qualified on N7-on-N7 this year with production targeted for 2022 at a new fully-automated factory.
For mobile applications, TSMC is introducing its InFO_B packaging technology to integrate a powerful mobile processor with DRAM stacking on the package.
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